FDC37B727-NS SMSC, FDC37B727-NS Datasheet - Page 114

IC CTRLR SUPER I/O ENH 128-QFP

FDC37B727-NS

Manufacturer Part Number
FDC37B727-NS
Description
IC CTRLR SUPER I/O ENH 128-QFP
Manufacturer
SMSC
Datasheet

Specifications of FDC37B727-NS

Controller Type
I/O Controller
Interface
ISA Host
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
30mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
128-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1005

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Part Number
Manufacturer
Quantity
Price
Part Number:
FDC37B727-NS
Manufacturer:
Standard
Quantity:
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Part Number:
FDC37B727-NS
Manufacturer:
Microchip Technology
Quantity:
10 000
(active), V
interface
PWRGOOD signal is “0” (inactive), V
and the FDC37B72x host interface is inactive;
that is, ISA bus reads and writes will not be
decoded.
The FDC37B72x device pins KDAT, MDAT,
IRRX, nRI1, nRI2, RXD1, RXD2, nRING,
Button_In and the GPIOs are part of the PME
interface and remain active as inputs for wakeup
when the internal PWRGOOD signal has gone
inactive, provided V
nPME/SCI, GP53/IRQ11 (SCI pin), nPowerOn
and CLK32OUT pins remain active as outputs
when the internal PWRGOOD is inactive and V
is powered. The internal PWRGOOD signal is
also used to disable the IR Half Duplex Timeout.
Note: If V
wake-up events when V
be at its full minimum potential at least 10 μs
before V
and V
between the two supplies must not exceed
500mV.
cc
are fully powered, the potential difference
cc
cc
TR
is
begins a power-on cycle. When V
is > 4V, and the FDC37B72x host
is to be used for programmable
active.
TR
is powered. In addition, the
CC
is removed, V
When
the
cc
is ≤ 4V,
TR
internal
must
TR
TR
114
32.768 kHz STANDBY CLOCK OUTPUT
The FDC37B72x provides a 32.768 kHz trickle
clock output pin. This output is active as long as
V
OSCILLATOR
Crystal Oscillator input.
connected externally on the XTAL1 and XTAL2
pins generates the 32.768kHz input clock.
Maximum clock frequency is 32.768kHz.
oscillator is also used as an internal clock source
for functions within the FDC37B72x.
There is a bit in the Ring Filter Select Register that
can be used to select the load capacitance of the
crystal to ensure accurate time keeping. This bit is
defined as follows: Bit 6 - XTAL_CAP. This bit is
used
capacitance (12pF vs. 6pF):
0=12pF (Default), 1=6pF.
TR
is present.
to
specify
the
32kHz
A 32.768kHz crystal
XTAL
load
This

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