Z16C3010AEC Zilog, Z16C3010AEC Datasheet - Page 12

• Manufacturer Part Number: Z16C3010AEC
• Description: IC 10MHZ CMOS USC 100-VQFP
• Manufacturer: Zilog
• Series: USC®r

Specifications of Z16C3010AEC

• Controller Type: USC Controller
• Interface: DMA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 7mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS007902-0708
PITACK Pulsed Interrupt Acknowledge (input, active Low)—
signal that indicates that an interrupt acknowledge cycle is in progress. The device is capa-
ble of returning an interrupt vector that may be encoded with the type of interrupt pending
during this acknowledge cycle. PITACK may be programmed to accept a single pulse or
double pulse acknowledge type. This programming is done in the BCR. With the double
pulse type selected, the first PITACK is recognized but no action takes place. The interrupt
vector is returned on the second pulse if the no vector option is not selected. The double
pulse type is compatible with 8X86 family microprocessors.
WAIT/RDY Wait/Data Ready (output, active Low)—
the data is available during a read cycle, when the device is ready to receive data during a
write cycle, and when a valid vector is available during an interrupt acknowledge cycle. It
may be programmed to function either as a Wait signal or a Ready signal using the state of
the A/
functions as a wait output and thus supports the READY function of 8X86 family micro-
processors. When A/B is Low during the BCR write, this signal functions as a ready out-
put and thus supports the DTACK function of 680X0 family microprocessors.
AD15–AD0 Address/Data Bus (bidirectional, active High, tri-state)—
carry addresses to, and data to and from, the device. When the 16-bit nonmultiplexed bus
is selected, AD15–AD0 carry data to and from the device. Addresses are provided using a
pointer within the device that is loaded with the desired register address. When selecting
the 8-bit nonmultiplexed bus (without separate address) only AD7–AD0 are used to trans-
fer data. The pointer is used for addressing, with AD15–AD8 unused. When selecting the
8-bit nonmultiplexed bus (with separate address), AD7–AD0 are used to transfer data with
AD15–AD8 used as address bus. When the 16-bit multiplexed bus is selected, addresses
are latched from AD7–AD0 and data transfers are sixteen bits wide. When selecting the 8-
bit multiplexed bus (without separate address) only AD7–AD0 are used to transfer
addresses and data, with AD15–AD8 unused. When the 8-bit multiplexed bus with sepa-
rate address is selected, only AD7–AD0 are used to transfer data, while AD15–AD8 are
used as an address bus.
INTA, INTB Interrupt Request (outputs, active Low)—
channel has an interrupt condition pending and is requesting service. These outputs are
NOT open-drain.
IEIA, IEIB Interrupt Enable In (inputs, active High)—
used with the accompanying IEO signal to form an interrupt daisy chain. An active IEI
indicates that no device having higher priority is requesting or servicing an interrupt.
IEOA, IEOB Interrupt Enable Out (outputs, active High)—
channel is used with the accompanying IEI signal to form an interrupt daisy chain. IEO is
Low if IEI is Low, an interrupt is under service in the channel, or an interrupt is pending
during an interrupt acknowledge cycle.
TxACKA, TxACKB Transmit Acknowledge (inputs or outputs, active Low)—
mary function of these signals is to perform fly-by DMA transfers to the transmit FIFOs.
They may also be used as bit inputs or outputs.
B
pin during the BCR write. When A/B is High during the BCR write, this signal
P R E L I M I N A R Y
This signal serves to indicate when
The IEI signal for each channel is
These signals indicate that the
The IEO signal for each
Product Specification
This signal is a strobe
The AD signals
Pin Description
Z16C30
The pri-
8