Z87L0116ASC Zilog, Z87L0116ASC Datasheet - Page 45

• Manufacturer Part Number: Z87L0116ASC
• Description: IC FHSS PHONE CTRL 144-VQFP
• Manufacturer: Zilog

Specifications of Z87L0116ASC

• Controller Type: Phone Controller
• Interface: Bus
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 55mA
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REGISTER DESCRIPTION (Continued)
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
RATE_BUF_DATA
Field
RX_BUF_DATA
TX_BUF_DATA
TX_BUF_VP_ADDR
RX_BUF_VP_ADDR
TX_RX_NIBBLE_MARKER fedcba9876543210
MOD_FREQ
Note:
The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register.
MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz.
These words are encoded as 2’s complement numbers.
The meaning and address for any RATE_BUF_DATA is set in the RATE_BUF_ADDR register.
MOD_FREQ. The unit for center frequency and frequency deviation words is 62.5 Hz.
These words are encoded as 2’s complement numbers.
BIT_SYNC
Field
INT_SYM_ERR1
SECOND_ORDER
45
Bank 1
Bit Position
fedcba9876543210
fedcba9876543210
Bank 1
Bit Position
------------3210
------------3210
--dcba98--------
----------543210
fedcba9876543210
Table 29. Bank 1 Register Description
Table 30. Bank 1 Register Description
EXT2
R/W
W
R
P R E L I M I N A R Y
XXXXh
XXXXh
Data
EXT1
R/W
W
W
W
W
W
R
Read access to the integrated symbol error from the bit
synchronizer’s second order loop
Reads error data bits [23..8] (bits [7..0] are in bank 0,
EXT6)
Write access to the bit synchronizer’s second-order loop
Writes second order loop’s 16-bit value
XXXXh
XXXXh
XXXXh
Data
XXh
XXh
Xh
Access to the Rx rate buffer data
Reads value at current RX_BUF_ADDR
address (0 to 23h)
Access to the Tx rate buffer data
Writes value at current TX_BUF_ADDR address
(0 to 23h)
Sets the initialization value of the Tx rate buffer
address used for ADPCM Processor accesses
Writes initialization value (TX_BUF_ADDR
address= 24h)
Sets the initialization value of the Rx rate buffer
address used for ADPCM Processor accesses
Writes initialization value (TX_BUF_ADDR
address= 24h)
Sets the Nibble Marker register for Tx and Rx
rate buffer accesses by ADPCM Processor
Write nibble marker value (TX_BUF_ADDR=
25h to 27h)
Access to modulator settings
Writes modulator setting value
(TX_BUF_ADDR=28h to 32h)
Description
Description
DS96WRL0800
Zilog