Z87L0116ASC Zilog, Z87L0116ASC Datasheet
Z87L0116ASC
Specifications of Z87L0116ASC
Related parts for Z87L0116ASC
Z87L0116ASC Summary of contents
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... The Z87001 uses a Zilog 16-bit fixed-point two’s comple- ment static CMOS Digital Signal Processor core as the phone and RF section controller. The Z87001’s DSP core processor further supports control of the RF section’ ...
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... Z87001’s DSP core. In combination with an RF section designed according to the system specifications, Zilog’s Z87010/Z87L10 ADPCM Processor, a standard 8-bit PCM telephone codec and minimal additional phone circuity, the Z87001 and its em- bedded software provide a total system solution. ...
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... Zilog FSK Demodulator RX ADC (downconverter, limiter discriminator, (1-bit) AFC, bit sync, frame sync, SNR VREF detector) DAC TX (4-bit) RXSW TXSW PAON RFEON SYLE ADC RSSI (8-bit) DAC PWLV (4-bit) ANT0 ANT1 HBSW RESETB TEST DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller ...
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... P19 addr3 GND addr2 P18 addr1 P17 addr0 P16 idata15 VDD idata14 37 P15 4 Z87001 Figure 3. 144 Pin QFP Pin Configuration Zilog VXDATA0 109 data0 VXDATA1 data1 VXDATA2 data2 VDD VXDATA3 data3 VXDATA4 data4 VXDATA5 data5 VXDATA6 VXDATA7 data6 CLKOUT ...
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... Zilog No Symbol 1 2,141 AGND 3 4,144 AV 5 VREF 6 RFEON 7,9,11,13,15,17,19, addr[15..0] 21,23,25,27,29,31, 136,138,140 8,12,14,16,20,22,24, P1[15..0] 28,30,32,36,37,39, 41,44,46 10,26,43,60,77,88, GND 109,128 18,34,51,68,86,102, 116,131 33,35,38,40,42,45, idata[15..0] 47,49,52,54,56,59, 61,63,66,69 48,50,53,55,57,58, P0[15..0] 62,64,65,67,70,72, 73,75,79,80 71,74,76,78,81,83, data[15..0] 85,89,91,93,96,98, 100,103,105,107 82,84 ANT[1..0] 87 TEST 90 HBSW 92 CLKOUT 94,95,97,99,101, VXDATA[7..0] ...
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... Halt/ single step control Master clock (16.384 MHz) Program address bus enable RF transmit enable DSP core clock RF synthesizer load enable Demodulator “on” indication RF receive enable RF transmit power level RF receive signal strength indicator Zilog Direction Input Input Input Output Output Output Output Output Input ...
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... Zilog ABSOLUTE MAXIMUM RATINGS Symbol Parameter Min Supply -0 Voltage(1) V Input Voltage(2) -0 Output Voltage(3) -0.5 V OUT T Operating -20 A Temperature T Storage -65 STG Temperature Notes: 1. Voltage on all pins with respect to GND. 2. Voltage on all inputs WRT VDD 3. Voltage on all outputs WRT VDD STANDARD TEST CONDITIONS The electrical characteristics listed below apply for the fol- lowing standard test conditions, unless otherwise noted ...
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... Operation (Z87001) Parameter Table 4. 3.3V 0.3V Operation (Z87L01) Parameter 0.7 V GND -0 Min Max 4.5 5.5 2 0.3 DD GND -0.3 0.8 -2.0 -0.5 4.0 12.0 0.5 -20 +70 Min Max 3.0 3 -1.0 -0.5 2.0 6.0 0.5 -20 +70 DS96WRL0800 Zilog Units Units ...
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... Zilog DC ELECTRICAL CHARACTERISTICS Conditions for DC characteristics are corresponding oper- ating conditions, and standard test conditions, unless oth- erwise specified. Symbol Parameter V Output High Voltage OH V Output High Voltage, ICE pins (1) V OHICE V Output Low Voltage OL1 V Output Low Voltage, GPIO (2) OL2 ...
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... DD 2.7 (AV =4.5V) 3.0 ( Typical Maximum 1 - 1.0 2.75 (40 c) (-20 c) 0.2 1.1 (40 c) (-20 c) 8.192 - 3.6 5 8.5 - 0.5 1000 1200 = 3.3V) 2.1 (AV = 3.6V 5V) 3.3 (AV = 5.5V DS96WRL0800 Zilog Units bit mW mW MHz ns MHz KOhm pF ...
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... Zilog CLK (16.384MHz) INPUT SIGNAL Table 8. 8-bit ADC (Temperature -20/+70 C) Parameter Resolution Integral non-linearity Differential non-linearity Power Dissipation (peak) Sample window Bandwidth Supply Range (= Z87L01 Z87001 Input voltage range Conversion time Aperture delay Aperture uncertainty Input resistance Input capacitance Notes: 1. 8-bit ADC only tested for 6-bit resolution. ...
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... Output load capacitance 12 Table 9. 4-bit DAC (Temperature: -20/+70 C) Minimum - - - - - 14 1.2 (70 c) 0.18 ( 0.2 AV 3.0 4 Typical Maximum Units 4 - bit 0.25 0.5 LSB 0.25 1 LSB - 22 24.1 mW (40 c) (-20 c) 1.0 1.1 mW (40 c) (-20 c) 19.1 75 0.6AV - 3.3 3.6 V 5.0 5.5 V 330 Ohm DS96WRL0800 Zilog ...
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... Zilog INPUT/OUTPUT PIN CHARACTERISTICS All digital pins (all pins except RX, TX, RSSI and PWLV) have an internal capaci- REF tance of 5 pF. AC ELECTRICAL CHARACTERISTICS Clocks, Reset and RF Interface No. Symbol 1 TpC MCLK input clock period (1) 2 TwC MCLK input clock pulse width 3 TrC, TfC ...
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... Processor to the Z87001. Table 11. Read Cycles Function Address Bus Data Bus Strobe Control Signal Read/Write Control Signal Ready Control Signal Table 12. Write Cycles Parameter Zilog Direction ADPCM Proc. to Z87001 Bidirectional ADPCM Proc. to Z87001 ADPCM Proc. to Z87001 Z87001 to ADPCM Proc. Min Max Units 10 ...
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... Zilog AC TIMING DIAGRAMS MCLK CLKOUT CODCLK MCLK RESETB PAON TXSW RXSW RFEON SYLE DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller TwC(2) TrC(3) TfC(3) TpC (1) TfCC(4) TrCC(4) TfCO(5) TrCO( TwR(6) TfRF(7) TrRF(7) Figure 7. Transceiver Output Signal Z87001/Z87L01 ...
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... Z87001/Z87L01 ROMless Spread Spectrum Cordless Phone Controller VXADD VXRWB VXSTRB VXDATA VXRDYB VXADD VXRWB VXSTRB VXDATA VXRDYB 16 TsAS(8) TaDrS(10) VXDATA Read Cycle TsAS(8) TwS(12) TsDwS(13) VXDATA Write Cycle Figure 8. Read/Write Cycle TImings Zilog ThSA(9) ThDrS(11) ThSA(9) ThDwS(14) DS96WRL0800 ...
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... Zilog VXADD VXRWB VXSTRB VXDATA VXRDYB VXADD VXRWB VXSTRB VXDATA VXRDYB Figure 9. Read/Write Cycle Timing with Wait StatE DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller TsAS(8) TaDrRY(15) VXDATA Read Cycle with Wait State TsAS(8) TwS(12) TsDwS(13) VXDATA Write Cycle with Wait State ...
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... P1[15..0] (input/output).General-purpose I/O port. Direc- tion is bit-programmable. Pins P114 and P115, when con- figured in input mode, also behave as individually maskable interrupt pins for the core processor (positive edge-triggered Zilog for hand- WAKEUP0 WAKEUP1 WAKEUP2 WAKEUP3 INT0 INT2 DS96WRL0800 ...
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... The base station transmits a frame of 144 bits while the handset receives The handset then transmits a frame of 148 bits while the base receives. 4ms frame 144 bits TX TDD switching guard time RX Figure 1. Basic Time Duplex Timing Zilog 148 bits RX TX DS96WRL0800 ...
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... The inversion is then reversed on the demodulated data. Since the data is packed in frames sent alternately from base and handset every 4 ms (TDD), additional synchroni- zation means are necessary. This is realized in a frame SNR Limiter- Bit Frame Sync Sync Rx Buffer AFC DS96WRL0800 Zilog ...
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... The carrier frequency is adjustable by the DSP core pro- cessor in order to provide additional frequency adjustment between base and handset. This is provided in case of a frequency offset too large for possible correction by the AFC. The modulator also includes bit inversion logic as dis- cussed in the receiver section Zilog DS96WRL0800 ...
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... Control of the RF power and adaptive power algorithm Control of the demodulator (bit synchronizer loop filter, AFC bias estimate filtering) Control of the modulator (carrier frequency) and adaptive frequency alignment Signalling between base and handset to support above features Buffer Spectral Shaping DS96WRL0800 Zilog ...
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... The mapping of the command status and data interfaces from the Z87010 side is given below. Address Interface (VXADD [2.0]) Transmit 1 rate buffer Receive 1 rate buffer Command 0 Status Zilog Data bus Address bus Data Strobe Read/Write Control Read Control Read Data /Write (VXDATA[7.0]) W ----3210 R ----3210 R 76543210 ...
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... IF signals. The software has access to this frequency through the MOD_FREQ register fields. Discriminator Output Second down- convertor, Discriminator Bias estimator BIAS_THRESHOLD BIAS_ERROR_DATA CORE_BIAS_DATA USE_CORE_BIAS Figure 5. AFC Loop and Processor Control “0” BIAS_ENABLE DSP Core Processor DS96WRL0800 Zilog ...
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... M. Simon (Dover 1973; oh 442). Its operation is summarized in the following block diagram. Bank EXT 3 EXT0 3 EXT2 2 EXT2 2 EXT4 Transition Detection Signed Error Error Magnitude Loop Filter division “by 1” Clock “by 64” Generator first order SECOND_ORDER INT_SYM_ERR0 INT_SYM_ERR1 BSYNC_GAIN DSP Core Processor DS96WRL0800 Zilog ...
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... On the base station, the UW_LOCATION should be set to 301 Zilog DS96WRL0800 ...
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... Every time the frame counter wraps around frame start indicator bit is set (FRAME_START_IND status field). The software must reset this “IND” bit by setting the FRAME_START_CLEAR field. If the FS_INT_ENABLE bit is set, frame starts also trigger interrupts to the DSP pro- cessor Zilog by programming the DS96WRL0800 ...
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... If the same ROM code is used on base and handset, the software can determine which station it runs on by reading the HAND_BASE_SEL bit, which reflects the state of the HBSW pin Zilog fields, RFTX_PWR_ON and fields, RFRX_PWR_ON ...
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... RFTX_PWR_OFF RFTX_POLARITY Modulator RFRX_PWR_ON RFRX_PWR_OFF RFRX_POLARITY DEMOD_PWR_ON DEMOD_PWR_OFF Demodulator Figure 8. RF interface Control Register RX_PWR_CTRL SSPSTATE CONFIG1 SSPSTATE MOD_PWR_CTRL RFRX_PWR_CTRL DEMOD_PWR_CTRL RFRX_PWR_CTRL RFTX_PWR_CTRL RFTX_PWR_CTRL SSP_STATUS Zilog RFEON SYLE PAON TX TXSW RXSW RX,VREF Bank Ext 2 EXT6 3 EXT2 3 EXT0 3 EXT2 2 EXT5 0 EXT7 2 EXT6 ...
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... TX_BUF_DATA; for more information, see Register Description) after each data write. This allows the DSP core to write successive nibbles without resetting the address each time Field Register Bank CONFIG1 3 3 VP_INOUT 2 VP_INOUT 2 DS96WRL0800 Zilog Ext EXT0 EXT2 EXT0 EXT0 ...
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... RX RATE BUFFER RX_BUF_VP_ADDR Address TX_RX_NIBBLE_ Decoder TX_BUF_VP_ADDR TX RATE BUFFER RX_BUF_ADDR RX_AUTO_INCR. TX_BUF_ADDR TX_AUTO_INCR. DSP Core Processor Z87001 MARKER Data ADPCM Proc. Interface Addr Ctrl VP_COMMAND VP_STATUS DS96WRL0800 Zilog ...
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... Bank Next EXT0 EXT0 EXT0 EXT0 EXT0 EXT1 EXT1 EXT1 EXT1 EXT1 the INTERRUPT_0_ENABLE Interrupt DSP Interrupt Number Vector INT0 3FFFh INT2 3FFDh Register Bank Ext EXT4 GPI00DIR 3 GPI00DATA 3 EXT5 GPI0IDIR 3 EXT6 GPI0IDATA 3 EXT7 CONTROL 1 EXT6 CONTROL 1 EXT6 DS96WRL0800 Zilog and ...
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... Zilog REGISTER DESCRIPTION The Z87001 DSP core processor has four banks of eight registers mapped in the core processor’s “external regis- ter” space, as summarized in the following table. BANK ADDRESS REGISTER Bank 3 EXT0 CONFIG1 EXT1 CONFIG2 EXT2 SSPSTATE EXT3 SSPSTATUS EXT4 GPIO0DIR ...
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... Defines the search window size (in bits) for windowed search mode (for Unique Word or SYNC_D words). R Returns 0 W 0000 Window size=1 0001 Window size = ••• 1111 Window size = 31 (1 15) Bias estimator threshold value R Returns 0 W XXh Sets the bias value Zilog DS96WRL0800 ...
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... Zilog Config 2 Field Bit Position ANTENNA_SW_DEFEAT f--------------- ANTENNA_SW_OFFSET -edcba98-------- SLEEP_PERIOD --------76543210 SLEEP_REMAINING --------76543210 Notes: 1. SLEEP_PERIOD. In sleep mode, the RFEON pin is active. Changes to this bit take effect immediately. 2. SLEEP_REMAINING. A non-zero value indicates that the Z87001 was awakened by a key press activating one of the wake-up pins on port 0 ...
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... Wake mode only 1 Sleep mode can be activated by GO_TO_SLEEP command Controls operation of the transceiver R/W 00* SMUX (bit inversion and ADPCM Processor access 01 disabled) 10 STMUX (bit inv. enabled; ADPCM Proc. access disabled) 11 Reserved TMUX (bit inversion and ADPCM Processor access enabled Zilog DS96WRL0800 ...
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... Zilog SSPSTATE Bank 3 Field Bit Position GO_TO_SLEEP --------------0 TX_ENABLE -----a---------- SYNC_SEARCH_WORD ------9--------- SYNC_SEARCH_MODE -------87------- HOP_ENABLE ---------6------ SYNC_ACQ_CLEAR ----------5----- FRAME_START_CLEAR -----------4---- SLEEP_WAKE ------------3--- MULTIPLEX_SWITCH -------------21- GO_TO_SLEEP ---------------0 Notes: 1. DBP_STOP_CLOCK. When this bit is set to 1, the ADPCM Processor clock (CLKOUT) is stopped within two clock periods. When this bit is set to 0, the ADPCM Processor clock restarts within two clock periods; in every case, the ADPCM Processor clock min- imum specifications for high time and low time are respected ...
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... Indicates start of a new frame start of new frame (1 written to 1 FRAME_START_CLR) W New frame started No effect R Returns effect Table 16. Bank 3 Register Description EXT4 R/W Data Description Independent control of Port 0 pin direction R/W ..0. Sets pin in input mode ..1. Sets pin in output mode Zilog Description DS96WRL0800 ...
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... Zilog GPIO0DATA Bank 3 Field Bit Position DATA0 fedcba9876543210 Notes: DATA0. The read value returns the actual pin values and does not depend on the pin directions (i.e. for output pins, the output value is returned unless a contention occurs). GPIO1DIR Bank 3 Field Bit Position ...
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... Initializes the value that the receive frame counter is set to on detection of the Unique Word Table 22. Bank 2 Register Description EXT2 R/W Data Access to the bias estimate from the AFC loop. R XXXXh Current bias estimate value W No effect Zilog Description Description Description DS96WRL0800 ...
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... Zilog RSSI Bank 2 Field Bit Position RESERVED fedcba98-------- RSSI_DATA -------76543210 Note: RSSI_DATA. This value is sampled once per frame (4ms) approximately at bit 72 (middle) of the received data. CORE_BIAS Bank 2 Field Bit Position RESERVED fed------------- CORE_BIAS_DATA ---cba9876543210 Notes: CORE_BIAS_DATA.This value is used if the USE_CORE_BIAS register field is set encoded as a 2’s complement number. ...
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... R Returns 0 W xXh Bits 6-0 of turn-on time (=(x modulo 128) -1) R Returns effect Determine internal power down of demodulator and turn off time of RXSW pin, referenced to the receive frame counter R Returns 0 W XXh Bits 6-0 of turn-off time (=(x modulo 128) - Zilog Description DS96WRL0800 ...
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... Zilog RFTX_PWR_CTRL Bank 2 Field Bit Position RFTX_POLARITY f--------------- RFTX_PWR_ON -edcba98-------- RESERVED --------7------- RFTX_PWR_OFF ---------6543210 Notes: 1. RFTX_PWR_ON, RFTX_PWR_OFF. Controls the PAON output pin, and thereby the external RF module’s transmitter. The turn-on and off times are given in number of transmitted bit periods and are referenced to the transmit Frame Counter. ...
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... Tx/Rx Nibble Marker bits [15..0] 27h Tx/Rx Nibble Marker bits [31..16] 28h Tx/Rx Nibble Marker bits [35..32] 29h MOD_FREQ_DEV 0 2Ah MOD_FREQ_DEV 1 2Bh MOD_FREQ_DEV 2 2Ch MOD_FREQ_DEV 3 2Dh MOD_FREQ_DEV 4 2Eh MOD_FREQ_DEV 5 2Fh MOD_FREQ_DEV 6 30h MOD_FREQ_DEV 7 31h MOD_FREQ_DEV 8 32h MOD_FREQ_DEV 9 ... MOD_CENTER_FREQ Illegal Zilog Description DS96WRL0800 ...
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... Read access to the integrated symbol error from the bit synchronizer’s second order loop R XXXXh Reads error data bits [23..8] (bits [7..0] are in bank 0, EXT6) Write access to the bit synchronizer’s second-order loop W XXXXh Writes second order loop’s 16-bit value Zilog Description Description DS96WRL0800 ...
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... Enables P00 as wake-up pin (if in input mode) Access to Tx power 4-bit DAC output data R/W Xh Sets output value Table 33. Bank 1 Register Description EXT7 R/W Data R Returns effect Description Returns 0 Must be left alone or written to 0000h (or unpredictable results may occur) Description Description DS96WRL0800 Zilog ...
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... Zilog Bank 0 Registers RESERVED Bank 0 Field Bit Position RESERVED fedcba9876543210 INT_SYM_ERR0 Bank 0 Field Bit Position RESERVED fedcba98-------- INT_SYM_ERR0 --------76543210 DS96WRL0800 ROMless Spread Spectrum Cordless Phone Controller Table 34. Bank 0 Register Description EXT0 EXT1 EXT2 EXT3 EXT4 EXT5 R/W Data R Returns effect Table 35. Bank 0 Register Description ...
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... Determines TXSW output pin turn-on time referenced to the transmit frame counter R Returns 0 W xXh Bits 6-0 of turn-on time (=(x modulo 128) -1) R Returns effect Determine TXSW output pin turn-off time referenced to the transmit frame counter R Returns 0 W xXh Bits 6-0 of turn-off time (=(x modulo 128) - Zilog Description DS96WRL0800 ...
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... Zilog INSTRUCTION SET DESCRIPTION Refer to Zilog’s Z89C00 User’s Manual, Chapter 5 (In- struction Set Features) and Chapter 6 (Assembly Lan- Instruction Description Opcode ABS Absolute Value 1001000 1001000 ADD Addition 1001001 1000001 1000100 1000101 1000011 1000001 1000000 AND Bitwise AND 1011001 ...
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... MPYS<src1>,<src2> [,<bank switch>] <hwregs>,<regind> <hwregs>,<regind>,<ban k switch> <regind>,<regind> <regind>,<regind>,<bank switch> NEG <cc>,A <cc> NOP None OR <dest>,<src> A, <pregs> A, <dregs> A, <limm> A, <memind> A, <direct> A, <regind> A, <hwregs> Zilog # # Words Cycles Example A A,D0 A,P0 A,@P1 A,@D0 124 ...
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... Zilog Instruction Description Opcode POP Pop value from stack 0001010 0000100 0000010 0000000 PUSH Push value onto stack 0001001 0000001 0000001 0000000 0000100 0100101 0000101 RET Return from subroutine 0000000 RL Rotate Left 1001000 1001000 RR Rotate Right 1001000 1001000 SCF Set C flag ...