Z87L0116ASC Zilog, Z87L0116ASC Datasheet - Page 25

• Manufacturer Part Number: Z87L0116ASC
• Description: IC FHSS PHONE CTRL 144-VQFP
• Manufacturer: Zilog

Specifications of Z87L0116ASC

• Controller Type: Phone Controller
• Interface: Bus
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 55mA
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

OPERATION (Continued)
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
Modulator Control
The MOD_FREQ fields specify the carrier center frequen-
cy (should be programmed to 2.508 MHz) and deviation for
the FSK signal (should be programmed to 32.58 kHz). In
addition, wave shaping is performed on bit transitions, in
order to satisfy FCC regulations. Up to four different inter-
mediate deviation values are programmable for each of
the two FSK states. The MOD_FREQ fields are program-
mable in units of 62.5 Hz.
BIAS_THRESHOLD
BIAS_ENABLE
BIAS_ERROR_DATA
CORE_BIAS_DATA
25
Table 1. AFC and Modulator Control Fields
Discriminator
Output
Field
CONFIG1
SSPSTATE
BIAS_ERROR
CORE_BIAS
In-phase
Matched
Filter
Mid-phase
Matched
Filter
Recovered
Bit clock
Register
Figure 6. Bit Synchronizer Loop and Processor Control
Bank
Transition
Detection
Error
Magnitude
Clock
Generator
3
3
2
2
EXT0
EXT2
EXT2
EXT4
P R E L I M I N A R Y
EXT
Loop Filter
first order
division
Bit Synchronizer
The bit synchronizer circuit is an implementation of the
Data-Transition-Tracking Loop (DTTL), best described in
“Telecommunications Systems Engineering”, by W. Lind-
sey and M. Simon (Dover 1973; oh. 9 p. 442). Its operation
is summarized in the following block diagram.
Signed
Error
“by 1”
“by 64”
SECOND_ORDER
BSYNC_GAIN
INT_SYM_ERR0
INT_SYM_ERR1
DSP Core
Processor
DS96WRL0800
Zilog