FDC37B787-NS SMSC, FDC37B787-NS Datasheet - Page 133

• Manufacturer Part Number: FDC37B787-NS
• Description: IC CTRLR SUPER I/O ENH 128-QFP
• Manufacturer: SMSC

Specifications of FDC37B787-NS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 70mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1006

Bit 0 of Port 92, which generates the nALT_RST
signal, is used to reset the CPU under program
control. This signal is AND’ed together externally
with the reset signal (nKBDRST) from the
keyboard controller to provide a software means
of resetting the CPU.
means of reset than is provided by the keyboard
controller. Writing a 1 to bit 0 in the Port 92
Register causes this signal to pulse low for a
minimum of 6µs, after a delay of a minimum of
14µs.
This provides a faster
8042
P21
0
0
1
1
nGATEA20
ALT_A20
135
0
1
0
1
Before
generated, bit 0 must be set to 0 either by a
system reset of a write to Port 92. Upon reset,
this signal is driven inactive high (bit 0 in the Port
92 Register is set to 0).
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is
set to 1, then a pulse is generated by writing a 1
to bit 0 of the Port 92 Register and this pulse is
AND’ed with the pulse generated from the 8042.
This pulse is output on pin KRESET and its
polarity is controlled by the GPI/O polarity
configuration.
System
nA20M
another
0
1
1
1
nALT_RST
pulse
can
be