FDC37B787-NS SMSC, FDC37B787-NS Datasheet - Page 117

• Manufacturer Part Number: FDC37B787-NS
• Description: IC CTRLR SUPER I/O ENH 128-QFP
• Manufacturer: SMSC

Specifications of FDC37B787-NS

• Controller Type: I/O Controller
• Interface: ISA Host
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 70mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1006

IRQSER Data Frame
Once a Start Frame has been initiated, the
FDC37B78x will watch for the rising edge of the
Start Pulse and start counting IRQ/Data Frames
from there.
clocks: Sample phase, Recovery phase, and
Turn-around phase. During the Sample phase
the FDC37B78x must drive the IRQSER (SIRQ
pin) low, if and only if, its last detected IRQ/Data
value was low. If its detected IRQ/Data value is
high, IRQSER must be left tri-stated. During the
Recovery phase the FDC37B78x must drive the
SERIRQ high, if and only if, it had driven the
IRQSER low during the previous Sample Phase.
Each IRQ/Data Frame is three
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During the Turn-around Phase the FDC37B78x
must tri-state the SERIRQ. The FDC37B78x will
drive the IRQSER line low at the appropriate
sample point if its associated IRQ/Data line is
low, regardless of which device initiated the Start
Frame.
The Sample Phase for each IRQ/Data follows the
low to high transition of the Start Frame pulse by
a number of clocks equal to the IRQ/Data Frame
times three, minus one. (e.g. The IRQ5 Sample
clock is the sixth IRQ/Data Frame, (6 x 3) - 1 =
17th clock after the rising edge of the Start
Pulse).