COM20019I-DZD SMSC, COM20019I-DZD Datasheet - Page 23

• Manufacturer Part Number: COM20019I-DZD
• Description: IC CTRLR ARCNET 2KX8 RAM 28-PLCC
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20019I-DZD

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 20mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1000-5

REGISTER
ADDRESS
PTR HIGH
ADDRESS
PTR LOW
SUB ADR
URATION
CONFIG-
NODE ID
STATUS
STATUS
SETUP1
NEXT ID
SETUP2
TENTID
Chapter 6
6.1
SMSC COM20019I
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
DIAG.
DATA
MICROSEQUENCER
The COM20019I contains an internal microsequencer which performs all of the control operations
necessary to carry out the ARCNET protocol. It consists of a clock generator, a 544 x 8 ROM, a program
counter, two instruction registers, an instruction decoder, a no-op generator, jump logic, and
reconfiguration logic.
The COM20019I derives a 625 kHz and a 312.5 kHz clock from the output clock of the Clock Multiplier.
These clocks provide the rate at which the instructions are executed within the COM20019I. The 625 kHz
clock is the rate at which the program counter operates, while the 312.5 kHz clock is the rate at which the
instructions are executed. The microprogram
is stored in the ROM and the instructions are fetched and then placed into the instruction registers. One
register holds the opcode, while the other holds the immediate data. Once the instruction is fetched, it is
decoded by the internal instruction decoder, at which point the COM20019I proceeds to execute the
instruction. When a no-op instruction is encountered, the microsequencer enters a timed loop and the
program counter is temporarily stopped until the loop is complete. When a jump instruction is encountered,
the program counter is loaded with the jump address from the ROM. The COM20019I contains an internal
reconfiguration timer which interrupts the microsequencer if it has timed out. At this point the program
counter is cleared and the MYRECON bit of the Diagnostic Status Register is set.
NXT ID7
RECON
RESET
RBUS-
MODE
RI/TRI
DATA
MSB
NID7
TMG
TID7
MY-
RD-
A7
D7
P1
X
NXT ID6
CCHEN
DUPID
AUTO-
FOUR
NAKS
FUNCTIONAL DESCRIPTION
NID6
TID6
X/RI
INC
A6
D6
X
X
NXT ID5
TXEN
RCV-
X/TA
NID5
Table 6.1 - Read Register Summary
TID5
ACT
A5
D5
X
X
X
X
DATASHEET
NXT ID4
TOKEN
RCV-
TID4
NID4
POR
ET1
ALL
D4
A4
X
X
X
Page 23
READ
NXT ID3
CKP3
TEST
EXC-
TID3
NID3
NAK
ET2
D3
EF
A3
X
X
SUB-AD2
RECON
TENTID
PLANE
BACK-
SYNC
CKP2
TID2
NID2
NXT
NO-
A10
ID2
D2
A2
SUB-AD1
SUB-AD1
NXT ID1
NEXTID
CKP1
RCN-
NEW
TID1
NID1
TMA
TM1
D1
A9
A1
SLOW-
RCM-
SUB-
SUB-
NID0
TID0
LSB
ARB
NXT
TM2
TTA
AD0
AD0
TA/
ID0
A8
A0
D0
X
Rev. 09-25-07
ADDR
07-0
07-1
07-2
07-3
07-4
00
01
02
03
04
05
06