KSZ8893MBL Micrel Inc, KSZ8893MBL Datasheet - Page 42

• Manufacturer Part Number: KSZ8893MBL
• Description: IC MANAGED SW 10/100 100-LFBGA
• Manufacturer: Micrel Inc

Specifications of KSZ8893MBL

• Controller Type: Ethernet Switch Controller
• Interface: MII, RMII, SNI
• Voltage - Supply: 3.1 V ~ 3.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFBGA
• Number Of Primary Switch Ports: 3
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: Yes
• Integrated Led Drivers: Yes
• Power Supply Type: Analog/Digital
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.5V
• Operating Supply Voltage (min): 3.1V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 576-1603 - EVAL KIT EXPERIMENTAL KSZ8893MQL
• Current - Supply: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 576-3090

The SNI interface is a bit wide data interface and therefore runs at the network bit rate (not encoded). An
additional signal on the transmit side indicates when data is valid. Similarly, the receive side has an indicator that
conveys when the data is valid.
For half duplex operation, the SCOL signal is used to indicate that a collision has occurred during transmission.
MII Management (MIIM) Interface
The KSZ8893MQL/MBL supports the IEEE 802.3 MII Management Interface, also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of
the KSZ8893MQL/MBL. An external device with MDC/MDIO capability is used to read the PHY status or
configure the PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u
Specification.
The MIIM interface consists of the following:
The MIIM Interface can operate up to a maximum clock speed of 5 MHz.
The following table depicts the MII Management Interface frame format.
December 2007
Read
Write
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom
controller to communicate with the KSZ8893MQL/MBL device.
MIIM registers [29, 31].
Preamble
32 1’s
32 1’s
Start of
Frame
01
01
Table 7. MII Management Interface Frame Format
Read/Write
OP Code
10
01
PHY
Address
Bits [4:0]
AAAAA
AAAAA
42
REG
Address
Bits [4:0]
RRRRR
RRRRR
TA
Z0
10
Data
Bits [15:0]
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
M9999-121007-1.5
Idle
Z
Z