CY7C63833-LTXC Cypress Semiconductor Corp, CY7C63833-LTXC Datasheet - Page 44

• Manufacturer Part Number: CY7C63833-LTXC
• Description: IC USB PERIPHERAL CTRLR 32VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB Peripheral Controllerr

Specifications of CY7C63833-LTXC

• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Controller Type: USB Peripheral Controller
• Interface: USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 40 mA
• Operating Supply Voltage: 4 V to 5.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16. Timer Registers
All timer functions of the enCoRe II are provided by a single timer block. The timer block is asynchronous from the CPU clock.
16.1 Registers
16.1.1 Free Running Counter
The 16 bit free-running counter is clocked by the Timer Capture Clock (TCAPCLK). It is read in software for use as a general purpose
time base. When the low order byte is read, the high order byte is registered. Reading the high order byte reads this register, allowing
the CPU to read the 16-bit value atomically (loads all bits at one time). The free-running timer generates an interrupt at 1024 μs rate
when clocked by a 4 MHz source. It also generates an interrupt when the free running counter overflow occurs every 16.384 ms (with
a 4 MHz source). This allows extending the length of the timer in software.
Table 16-1. Free Running Timer Low order Byte (FRTMRL) [0x20] [R/W]
Table 16-2. Free Running Timer High-order Byte (FRTMRH) [0x21] [R/W]
Document 38-08035 Rev. *N
Bit [7:0]: Free running Timer [7:0]
This register holds the low order byte of the 16-bit free running timer. Reading this register causes the high order byte to be
moved into a holding register allowing an automatic read of all 16 bits simultaneously.
For reads, the actual read occurs in the cycle when the low order is read. For writes, the actual time the write occurs is the cycle
when the high order is written.
When reading the Free Running Timer, the low order byte must be read first and the high order second. When writing, the low
order byte must be written first then the high order byte.
Bit [7:0]: Free-running Timer [15:8]
When reading the Free-running Timer, the low order byte must be read first and the high order second. When writing, the low
order byte must be written first then the high order byte.
Read/Write
Read/Write
Default
Default
Field
Field
Bit #
Bit #
R/W
R/W
7
0
7
0
Tim er C apture
C lock
Figure 16-1. 16-Bit Free Running Counter Block Diagram
R/W
R/W
6
0
6
0
R unning C ounter
R/W
R/W
5
0
5
0
16-bit Free
Free-running Timer [15:8]
Free running Timer [7:0]
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Interrupt/W rap
1024µs T im er
O verflow
Interrupt
Interrupt
R/W
R/W
CY7C63310, CY7C638xx
2
0
2
0
R/W
R/W
1
0
1
0
Page 44 of 86
R/W
R/W
0
0
0
0
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