CY7C63803-SXC Cypress Semiconductor Corp, CY7C63803-SXC Datasheet - Page 83

• Manufacturer Part Number: CY7C63803-SXC
• Description: IC USB PERIPHERAL CTRLR 16-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB Interface ICr

Specifications of CY7C63803-SXC

• Package / Case: 16-SOIC (3.9mm Width)
• Controller Type: USB Peripheral Controller
• Interface: PS2, USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Operating Temperature Range: 0 C to + 70 C
• Propagation Delay Time Ns: 50 ns
• Resistance: 4 Ohms to 12 Ohms
• Supply Current: 10 mA
• Watchdog: Yes
• Operating Supply Voltage: 4.35 V to 5.25 V
• Core Size: 8 Bit
• No. Of I/o's: 14
• Program Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 1
• Embedded Interface Type: PS/2, USB
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2914-5; CY7C63803-SXC

34. Document History Page
Document 38-08035 Rev. *N
Revision
Document Title: CY7C63310, CY7C638xx enCoRe™ II Low Speed USB Peripheral Controller
Document Number: 38-08035
*C
*D
*A
*B
*E
*F
**
ECN No.
131323
221881
271232
299179
322053
341277
408017
Change
Orig. of
XGR
BON
BON
BON
KKU
TVR
BHA
TYJ
sion Date
See ECN
See ECN
See ECN
See ECN
See ECN
See ECN
Submis-
12/11/03
New data sheet
Added Register descriptions and package information, changed from advance
information to preliminary
Reformatted. Updated with the latest information
Corrected 24-PDIP pinout typo in
page 22.
page
54. and
(General Purpose I/O (GPIO) Ports on page
43. Corrected
16-pin PDIP package diagram (section
Introduction on page
no LVR, only LVD (Low voltage detect). Explained more about LVD and POR.
Changed capture pins from P0.0,P0.1 to P0.5,P0.6.
Table 6-1 on page
as Register names).
Table 9-5 on page
Clock Architecture Description on page
options from n=0-5,7,8 to n=0-5,7.
Clocking on page
sources to ITMRCLK, TCAPCLKs. Mentioned P17 is TTL enabled permanently.
Corrected FRT, PIT data write order. Updated INTCLR, INTMSK registers in the
register table also.
DC Characteristics on page
programmable trip points based on char data. Updated the 50ma sink pins on
638xx, 63903. Keep-alive voltage mentioned corresponding to Keep-alive
current of 20uA. Included Notes regarding VOL,VOH on P1.0,P1.1 and TMDO
spec.
AC Characteristics on page
Phase to 0.
Pinouts on page
Removed SCLK and SDATA. Created a separate pinout diagram for the
CY7C63813.
Added the GPIO Block Diagram
Table 10-4 on page
to Hz.
Table 21-1 on page
Corrected V
Updated V
Added footnote to pin description table for D+/D– pins.
Added Typical Values to Low Voltage Detect table.
Corrected Pin label on 16-pin PDIP package.
Corrected minor typos.
Table 5-2 on page
- GPIO port 3
New Assignments: Pin 19 assigned to P3.0 and pin 20 to P3.1
Table 17-6 on page
Table 17-7 on page
Register Summary on page
INT_MASK0 and address E1 assigned to INT_MASK1
32,
Table 15-2 on page
Updated
Table 17-1 on page
IL
IH
TTL value.
Figure 28-7 on page 74
TTL value in
5: Removed the VREG from the CY7C63310 and CY7C63801
20: Changed ITMRCLK division to 1,2,3,4. Updated the
Table 9-5 on page
8: Changed table heading (Removed Mnemonics and made
7: Corrected pin assignment for the 24-pin QSOP package
17: Included #of rows for different flash sizes.
24: Changed the Sleep Timer Clock unit from 32 kHz count
59: Added more descriptions to the register.
55: INT_MASK1 changed to 0xE1
56: INT_MASK0 changed to 0xE0
4: Removed Low-voltage reset in last paragraph. There is
Description of Change
DC Characteristics on page
70: T
42. Added various updates to the GPIO Section
65: Register Summary, address E0 assigned to
69: changed LVR to LVD included max min
53,
(Figure 14-1 on page
Table 17-3 on page
MDO1
Table 5-2 on page 7
17,
and
CY7C63310, CY7C638xx
, T
Package Diagrams on page
22: Changed CPUCLK selectable
Table 10-3 on page
SDO1
Figure 28-8 on page 74.
34) Corrected
In description column changed
53,
37)
Added
69.
Table 17-5 on page
Table 15-4 on page
23,
Table 10-1 on
Table 13-1 on
Page 83 of 86
Added the
77)
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