CY7C63803-SXC Cypress Semiconductor Corp, CY7C63803-SXC Datasheet - Page 30

• Manufacturer Part Number: CY7C63803-SXC
• Description: IC USB PERIPHERAL CTRLR 16-SOIC
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB Interface ICr

Specifications of CY7C63803-SXC

• Package / Case: 16-SOIC (3.9mm Width)
• Controller Type: USB Peripheral Controller
• Interface: PS2, USB
• Voltage - Supply: 4 V ~ 5.5 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 8
• Operating Temperature Range: 0 C to + 70 C
• Propagation Delay Time Ns: 50 ns
• Resistance: 4 Ohms to 12 Ohms
• Supply Current: 10 mA
• Watchdog: Yes
• Operating Supply Voltage: 4.35 V to 5.25 V
• Core Size: 8 Bit
• No. Of I/o's: 14
• Program Memory Size: 8KB
• Ram Memory Size: 256Byte
• Cpu Speed: 24MHz
• No. Of Timers: 1
• Embedded Interface Type: PS/2, USB
• Digital Ic Case Style: SOIC
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY4623 - KIT MOUSE REFERENCE DESIGN428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2914-5; CY7C63803-SXC

12.1 Sleep Sequence
The SLEEP bit is an input into the sleep logic circuit. This circuit
is designed to sequence the device into and out of the hardware
sleep state. The hardware sequence to put the device to sleep
is shown in
12.2 Wake up Sequence
Once asleep, the only event that can wake the system up is an
interrupt. The global interrupt enable of the CPU flag register is
not required to be set. Any unmasked interrupt wakes the system
up. It is optional for the CPU to actually take the interrupt after
the wake up sequence. The wake up sequence is synchronized
to the 32 kHz clock for purposes of sequencing a startup delay,
to allow the flash memory module enough time to power up
before the CPU asserts the first read access. Another reason for
the delay is to allow the oscillator, Bandgap, and LVD/POR
circuits time to settle before actually being used in the system.
As shown in
as follows:
Document 38-08035 Rev. *N
1. Firmware sets the SLEEP bit in the CPU_SCR0 register. The
2. Due to the specific timing of the register write, the CPU issues
1. The wake up interrupt occurs and is synchronized by the neg-
2. At the following positive edge of the 32 kHz clock, the system
Bus Request (BRQ) signal to the CPU is immediately
asserted. This is a request by the system to halt CPU
operation at an instruction boundary. The CPU samples BRQ
on the positive edge of CPUCLK.
a Bus Request Acknowledge (BRA) on the following positive
ative edge of the 32 kHz clock.
wide PD signal is negated. The flash memory module, internal
oscillator, EFTB, and bandgap circuit are all powered up to a
normal operating state.
Figure 12-1
Figure 12-2 on page
Firmware write to SCR
SLEEP bit causes an
and is defined as follows.
immediate BRQ
CPUCLK
SLEEP
BRQ
BRA
IOW
PD
31, the wake up sequence is
CPU captures BRQ
on next CPUCLK
Figure 12-1. Sleep Timing
edge
responds with
3. The system wide PD (power down) signal controls several
3. At the following positive edge of the 32 kHz clock, the current
4. At the following negative edge of the 32 kHz clock (after about
edge of the CPU clock. The sleep logic waits for the following
negative edge of the CPU clock and then asserts a system
wide Power Down (PD) signal. In
CPU is halted and the system wide power down signal is
asserted.
major circuit blocks: The flash memory module, the internal
24 MHz oscillator, the EFTB filter and the bandgap voltage
reference. These circuits transition into a zero power state.
The only operational circuits on chip are the Low Power
oscillator, the bandgap refresh circuit, and the supply voltage.
monitor. (POR/LVD) circuit.
values for the precision POR and LVD have settled and are
sampled.
15 µS nominal), the BRQ signal is negated by the sleep logic
circuit. On the following CPUCLK, BRA is negated by the CPU
and instruction execution resumes. Note that in
on page 31
oscillator, EFTB, and bandgap, have about 15 µSec start up.
The wakeup times (interrupt to CPU operational) range from
75 µS to 105 µS.
a BRA
CPU
fixed function blocks, such as flash, internal
system clock is halted; the Flash
and bandgap are powered down
On the falling edge of CPUCLK,
PD is asserted. The 24/48 MHz
CY7C63310, CY7C638xx
Figure 12-1 on page 30
Page 30 of 86
Figure 12-2
the
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