UDA1380TT/N2,512 NXP Semiconductors, UDA1380TT/N2,512 Datasheet - Page 57

• Manufacturer Part Number: UDA1380TT/N2,512
• Description: IC AUDIO CODER-DECODER 32-TSSOP
• Manufacturer: NXP Semiconductors
• Type: Stereo Audior

Specifications of UDA1380TT/N2,512

• Package / Case: 32-TSSOP
• Data Interface: I²C, Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 100
• Voltage - Supply, Analog: 2.4 V ~ 3.6 V
• Voltage - Supply, Digital: 2.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Interface Type: Serial (I2C)
• Resolution: 24 bit
• Operating Supply Voltage: 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Current: 10 mA
• Thd Plus Noise: - 85 dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270659512; UDA1380TT; UDA1380TT

NXP Semiconductors
Notes
1. The typical value of the timing is specified at 48 kHz sampling frequency (see Fig.16).
2. T
3. In order to prevent digital noise interfering with the L3-bus communication, it is best to have the rise and fall times as
4. When the sampling frequency is below 32 kHz, the L3CLOCK cycle must be limited to
5. C
6. After this period, the first clock pulse is generated.
7. To be suppressed by the input filter.
2004 Apr 22
t
t
t
t
t
I
f
t
t
t
t
t
t
t
t
t
t
t
C
stp(L3)
su(L3)DA
h(L3)DA
d(L3)R
dis(L3)R
2
SCL
LOW
HIGH
r
f
HD;STA
SU;STA
SU;STO
BUF
SU;DAT
HD;DAT
SP
C-bus interface timing; see Fig.20
Stereo audio coder-decoder
for MD, CD and MP3
b
SYMBOL
short as possible.
cy(s)
b
is the total capacitance of one bus line in pF. The maximum capacitive load for each bus line is 400 pF.
is the cycle time of the sample frequency.
L3MODE stop time in data transfer
mode
L3DATA set-up time in address and
data transfer mode
L3DATA hold time in address and
data transfer mode
L3DATA delay time in data transfer
mode
L3DATA disable time for read data
SCL clock frequency
SCL LOW time
SCL HIGH time
rise time SDA and SCL
fall time SDA and SCL
hold time START condition
set-up time repeated START
set-up time STOP condition
bus free time between a STOP and
START condition
data set-up time
data hold time
pulse width of spikes
capacitive load for each bus line
PARAMETER
note 5
note 5
note 6
note 7
CONDITIONS
57
190
190
30
0
0
0
1.3
0.6
20 + 0.1C
20 + 0.1C
0.6
0.6
0.6
1.3
100
0
0
−
MIN.
b
b
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
TYP.
1
⁄
64fs
cycle.
−
−
−
50
50
400
−
−
300
300
−
−
−
−
−
−
50
400
Product specification
MAX.
UDA1380
ns
ns
ns
ns
ns
kHz
μs
μs
ns
ns
μs
μs
μs
μs
ns
μs
ns
pF
UNIT