AD1843JS Analog Devices Inc, AD1843JS Datasheet - Page 35

• Manufacturer Part Number: AD1843JS
• Description: IC CODEC STEREO 5V 16BIT 80PQFP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of AD1843JS

• Rohs Status: RoHS non-compliant
• Data Interface: Serial
• Resolution (bits): 16 b
• Number Of Adcs / Dacs: 1 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 92 / 86
• Dynamic Range, Adcs / Dacs (db) Typ: 85 / 80
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 2.85 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-MQFP, 80-PQFP

REV. 0
LDA1AM
LDA1A5:0
RDA1AM
RDA1A5:0
res
LDA2AM
LDA2A5:0
RDA2AM
RDA2A5:0
res
Address 11
Address 12
RDA1AM
RDA2AM
LDA1AM
LDA2AM
Data 15
Data 15
Data 7
Data 7
Left DAC1 Digital Mute
0 = Left DAC1 Enabled
1 = Left DAC1 Muted
Left DAC1 Digital Attenuation Select. Least significant bit represents –1.5 dB.
000000 = +0.0 dB Attenuation
111111 = –94.5 dB Attenuation
Right DAC1 Digital Mute
0 = Right DAC1 Enabled
1 = Right DAC1 Muted
Right DAC1 Digital Attenuation Select. Least significant bit represents –1.5 dB.
000000 = +0.0 dB Attenuation
111111 = –94.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled).
Left DAC2 Digital Mute
0 = Left DAC2 Enabled
1 = Left DAC2 Muted
Left DAC2 Digital Attenuation Select. Least significant bit represents –1.5 dB.
000000 = +0.0 dB Attenuation
111111 = –94.5 dB Attenuation
Right DAC2 Digital Mute
0 = Right DAC2 Enabled
1 = Right DAC2 Muted
Right DAC2 Digital Attenuation Select. Least significant bit represents –1.5 dB.
000000 = +0.0 dB Attenuation
111111 = –94.5 dB Attenuation
Reserved for future expansion. To ensure future compatibility, write “0” to all reserved bits.
Initial default state after reset: 0000 0000 0000 0000 (0000 hex). Cleared to default and cannot be written to when:
the RESET pin is asserted LO; when the PWRDWN pin is asserted LO; or when the PDNO bit in Control Register
Address 0 is set to “1” (all conversions disabled).
Data 14
Data 14
Data 6
Data 6
res
res
res
res
Output Control—DAC1 Digital Attenuation
Output Control—DAC2 Digital Attenuation
LDA1A5
RDA1A5
LDA2A5
RDA2A5
Data 13
Data 13
Data 5
Data 5
LDA1A4
RDA1A4
LDA2A4
RDA2A4
Data 12
Data 12
Data 4
Data 4
–35–
LDA1A3
RDA1A3
LDA2A3
RDA2A3
Data 11
Data 11
Data 3
Data 3
LDA1A2
RDA1A2
LDA2A2
RDA2A2
Data 10
Data 10
Data 2
Data 2
LDA1A1
RDA1A1
LDA2A1
RDA2A1
Data 9
Data 1
Data 9
Data 1
LDA1A0
RDA1A0
LDA2A0
RDA2A0
Data 8
Data 0
Data 8
Data 0
AD1843