EMC2300-AZC-TR SMSC, EMC2300-AZC-TR Datasheet - Page 48

• Manufacturer Part Number: EMC2300-AZC-TR
• Description: Industrial Temperature Sensors Auto Fan Contrllr Up to 4 Fans
• Manufacturer: SMSC

Specifications of EMC2300-AZC-TR

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Addr
Reg
FFh
88h
90h
91h
92h
93h
94h
95h
96h
/Write
Read
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Note: SMSC Test Registers may be read/write registers. Writing these registers can cause unwanted results.
Note 8.1
Note 8.2
Note 8.3
Note 8.4
Note 8.5
Note 8.6
Note 8.7
A/D Converter LSbs Reg 4
SMSC Test Register
The PWMx Current Duty Cycle Registers are only writable when the associated fan is in manual mode. In this case, the register is writable
when the start bit is set, but not when the lock bit is set.
The Lock bit in the Ready/Lock/Start register is locked by the Lock Bit. The START and OVRID bits are always writable, both when the start
bit is set and when the lock bit is set.
The Interrupt status registers are cleared on a read if no events are active
The INTEN bit in register 7Ch is always writable, both when the start bit is set and when the lock bit is set.
In Shutdown Mode (LPMD=1 & START=0) all the H/W Monitoring registers/bits are not accessible except for the following: Bits[2:0] in the
Special Function Register (SFTR) at offset 7Ch and Bits[7:0] in the Configuration register at offset 7Fh.
These Reserved bits are read/write bits. Writing these bits to a ‘1’ has no effect on the hardware.
SMSC bits may be read/write bits. Writing these bits to a value other than the default value may cause unwanted results
PWM1 Option
PWM2 Option
PWM3 Option
Tach1 Option
Tach2 Option
Tach3 Option
Tach4 Option
Reg Name
Note 8.6
Note 8.6
Note 8.6
VCC.3
Table 8.1 Register Summary (continued)
TST7
Bit 7
MSb
RES
RES
RES
RES
RES
RES
RES
Note 8.6
Note 8.6
Note 8.6
VCC.2
TST 6
RE S
Bit 6
RES
RES
RES
RES
RES
RES
VCC.1
TST 5
Bit 5
RES
RES
RES
RES
OPP
OPP
OPP
VCC.0
3EDG
3EDG
3EDG
3EDG
GRD1
GRD1
GRD1
TST 4
Bit 4
MODE
MODE
MODE
MODE
VCP.3
GRD0
GRD0
GRD0
TST3
Bit 3
VCP.2
EDG1
EDG1
EDG1
EDG1
SZEN
SZEN
SZEN
TST2
Bit 2
UPDT1
UPDT1
UPDT1
VCP.1
EDG0
EDG0
EDG0
EDG0
TST1
Bit 1
UPDT0
UPDT0
UPDT0
SLOW
SLOW
SLOW
SLOW
VCP.0
TST0
Bit 0
LSb
Default
Value
0Ch
0Ch
0Ch
N/A
04h
04h
04h
04h
N/A
Lock
Yes
Yes
Yes
No
No
No
No
No
No
Start
No
No
No
No
No
No
No
No
No