ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 31

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Digital Microphone Input
When using a digital microphone connected to the JACKDET/
MICIN pin, the JDFUNC[1:0] bits in Register R2 (Address 0x4008)
must be set to 10 to enable the microphone input and disable
the jack detection function. The ADAU1361 must operate in
master mode and source BCLK to the input clock of the digital
microphone.
The digital microphone signal bypasses record path mixers and
ADCs and is routed directly into the decimation filters. The
digital microphone and ADCs share decimation filters and,
therefore, both cannot be used simultaneously. The digital
microphone input select bit, INSEL, can be set in Register R19
(ADC control register, Address 0x4019). Figure 35 depicts the
digital microphone interface and signal routing.
Microphone Bias
The MICBIAS pin provides a voltage reference for electret analog
microphones. The MICBIAS voltage is set in Register R10
(record microphone bias control register, Address 0x4010). In
this register, the MICBIAS output can be enabled or disabled.
Additional options include high performance operation and a
gain boost. The gain boost provides two different voltage biases:
0.65 × AVDD or 0.90 × AVDD. When enabled, the high perfor-
mance bit increases supply current to the microphone bias
circuit to decrease rms input noise.
The MICBIAS pin can also be used to cleanly supply voltage
to digital microphones or analog microphones with separate
power supply pins.
RIGHT
LEFT
ADC
ADC
Figure 35. Digital Microphone Interface Block Diagram
DETECTION
TO JACK
CIRCUIT
DECIMATORS
JACKDET/MICIN
DIGITAL MICROPHONE
CHANNEL
LEFT
INTERFACE
CHANNEL
RIGHT
R2: DIGITAL MICROPHONE/
R19: ADC CONTROL
JACK DETECTION
JDFUNC[1:0]
CONTROL
INSEL
Rev. C | Page 31 of 80
ANALOG-TO-DIGITAL CONVERTERS
The ADAU1361 uses two 24-bit Σ-Δ analog-to-digital con-
verters (ADCs) with selectable oversampling ratios of 64× or
128× (selected by Bit 3 in Register R17, Address 0x4017).
ADC Full-Scale Level
The full-scale input to the ADCs (0 dBFS) depends on AVDD.
At AVDD = 3.3 V, the full-scale input level is 1.0 V rms. This
full-scale analog input will output a digital signal at −1.38 dBFS.
This gain offset is built into the ADAU1361 to prevent clipping.
The full-scale input level scales linearly with the level of AVDD.
For single-ended and pseudo-differential signals, the full-scale
value corresponds to the signal level at the pins, 0 dBFS.
The full differential full-scale input level is measured after the
differential amplifier, which corresponds to −6 dBFS at each pin.
Signal levels above the full-scale value cause the ADCs to clip.
Digital ADC Volume Control
The digital ADC volume can be attenuated using Register R20 (left
input digital volume register, Address 0x401A) and Register R21
(right input digital volume register, Address 0x401B).
High-Pass Filter
By default, a high-pass filter is used in the ADC path to remove
dc offsets; this filter can be enabled or disabled in Register R19
(ADC control register, Address 0x4019). At f
corner frequency of this high-pass filter is 2 Hz.
S
= 48 kHz, the
ADAU1361