ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 27

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PLL
The PLL uses the MCLK as a reference to generate the core
clock. PLL settings are set in Register R1 (PLL control register,
Address 0x4002). Depending on the MCLK frequency, the PLL
must be set for either integer or fractional mode. The PLL can
accept input frequencies in the range of 8 MHz to 27 MHz.
All six bytes in the PLL control register must be written with a
single continuous write to the control port.
Integer Mode
Integer mode is used when the MCLK is an integer (R) multiple
of the PLL output (1024 × f
For example, if MCLK = 12.288 MHz and f
In integer mode, the values set for N and M are ignored.
Table 15. PLL Control Register (Register R1, Address 0x4002)
Bits
[47:32]
[31:16]
[14:11]
[10:9]
8
1
0
PLL required output = 1024 × 48 kHz = 49.152 MHz
R = 49.152 MHz/12.288 MHz = 4
MCLK
Bit Name
M[15:0]
N[15:0]
R[3:0]
X[1:0]
Type
Lock
PLLEN
Figure 30. PLL Block Diagram
÷ X
S
).
× (R + N/M)
Description
Denominator of the fractional PLL: 16-bit binary number
0x00FD: M = 253 (default)
Numerator of the fractional PLL: 16-bit binary number
0x000C: N = 12 (default)
Integer part of PLL: four bits, only values 2 to 8 are valid
0010: R = 2 (default)
0011: R = 3
0100: R = 4
0101: R = 5
0110: R = 6
0111: R = 7
1000: R = 8
PLL input clock divider
00: X = 1 (default)
01: X = 2
10: X = 3
11: X = 4
PLL operation mode
0: Integer (default)
1: Fractional
PLL lock (read-only bit)
0: PLL unlocked (default)
1: PLL locked
PLL enable
0: PLL disabled (default)
1: PLL enabled
CLOCK DIVIDER
S
TO PLL
= 48 kHz, then
Rev. C | Page 27 of 80
Fractional Mode
Fractional mode is used when the MCLK is a fractional
(R + (N/M)) multiple of the PLL output.
For example, if MCLK = 12 MHz and f
Common fractional PLL parameter settings for 44.1 kHz and
48 kHz sampling rates can be found in Table 16 and Table 17.
The PLL outputs a clock in the range of 41 MHz to 54 MHz,
which should be taken into account when calculating PLL
values and MCLK frequencies.
PLL required output = 1024 × 48 kHz = 49.152 MHz
R + (N/M) = 49.152 MHz/12 MHz = 4 + (12/125)
S
= 48 kHz, then
ADAU1361