ADAU1328BSTZ Analog Devices Inc, ADAU1328BSTZ Datasheet - Page 25

• Manufacturer Part Number: ADAU1328BSTZ
• Description: IC CODEC 24BIT 2ADC/8DAC 48LQFP
• Manufacturer: Analog Devices Inc
• Type: General Purposer

Specifications of ADAU1328BSTZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 8
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 94 / 94
• Dynamic Range, Adcs / Dacs (db) Typ: 105 / 106
• Voltage - Supply, Analog: 3 V ~ 3.6 V
• Voltage - Supply, Digital: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 8
• No. Of Input Channels: 2
• No. Of Output Channels: 8
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 108dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 16. PLL and Clock Control 1
Bit
0
1
2
3
7:4
DAC CONTROL REGISTERS
Table 17. DAC Control 0
Bit
0
2:1
5:3
7:6
Table 18. DAC Control 1
Bit
0
2:1
3
4
5
6
7
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Value
0
1
0
1
0
1
0
1
0000
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Function
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
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Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read-only)
Description
Power-down
Sample rate
SDATA delay (BCLK periods)
Serial format
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
ADAU1328