ADAU1328BSTZ Analog Devices Inc, ADAU1328BSTZ Datasheet
ADAU1328BSTZ
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ADAU1328BSTZ Summary of contents
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FEATURES PLL generated or direct master clock Low EMI design 108 dB DAC/107 dB ADC dynamic range and SNR −94 dB THD + N Single 3.3 V supply Tolerance for 5 V logic inputs Supports 24 bits and 8 kHz ...
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ADAU1328 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Test Conditions............................................................................. 3 Analog Performance Specifications ........................................... 3 Crystal Oscillator Specifications................................................. 4 Digital Input/Output Specifications........................................... 4 ...
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SPECIFICATIONS TEST CONDITIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply Voltages (AVDD, DVDD) 3 Temperature Range As specified in Table 1 Master Clock 12.288 MHz (48 kHz ...
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ADAU1328 Parameter Interchannel Phase Deviation Volume Control Step Volume Control Range De-emphasis Gain Error Output Resistance at Each Pin REFERENCE Internal Reference Voltage External Reference Voltage Common-Mode Reference Output CRYSTAL OSCILLATOR SPECIFICATIONS Table 2. Parameter Transconductance DIGITAL INPUT/OUTPUT SPECIFICATIONS −40°C ...
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POWER SUPPLY SPECIFICATIONS Table 4. Parameter SUPPLIES Voltage Digital Current Normal Operation Power-Down Analog Current Normal Operation Power-Down DISSIPATION Operation All Supplies Digital Supply Analog Supply Power-Down, All Supplies POWER SUPPLY REJECTION RATIO Signal at Analog Supply Pins Conditions/Comments DVDD ...
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ADAU1328 DIGITAL FILTERS Table 5. Parameter ADC DECIMATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay TIMING SPECIFICATIONS −40°C < ...
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Parameter SPI PORT t CCH t CCL f CCLK t CDS t CDH t CLS t CLH t CLHIGH t COE t COD t COH t COTS DAC SERIAL PORT t DBH t DBL t DLS t DLH t DLS ...
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ADAU1328 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Analog (AVDD) Digital (DVDD) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute Maximum ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND MCLKI/XI MCLKO/XO AGND AVDD OL3 OR3 OL4 OR4 PD/RST DSDATA4 DGND Table 9. Pin Function Description Pin No. In/Out Mnemonic 1 I AGND 2 I MCLKI/ MCLKO/ AGND 5 I ...
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ADAU1328 Pin No. In/Out Mnemonic 26 I CCLK/SCL 27 I CLATCH/ADR1 28 O OL1 29 O OR1 30 O OL2 31 O OR2 32 I AGND 33 I AVDD 34 I AGND 35 O FILTR 36 I AGND 37 I ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –0.08 –0.10 0 2000 4000 6000 8000 10000 12000 FREQUENCY (Hz) Figure 3. ADC Pass-Band Filter Response, 48 kHz 0 –10 –20 –30 –40 –50 –60 –70 –80 ...
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ADAU1328 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 –0 FREQUENCY (kHz) Figure 9. DAC Pass-Band Filter Response, 192 kHz Rev Page –2 –4 –6 –8 ...
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THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTERS (ADCs) There are two ADC channels in the ADAU1328 configured as two stereo pairs with differential inputs. The ADCs can operate at a nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ...
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ADAU1328 To maintain the highest performance possible recommended that the clock jitter of the internal master clock signal be limited to less than 300 ps rms time interval error (TIE). Even at these levels, extra noise or tones ...
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POWER SUPPLY AND VOLTAGE REFERENCE The ADAU1328 is designed for 3.3 V supplies. Separate power supply pins are provided for the analog and digital sections. These pins should be bypassed with 100 nF ceramic chip capacitors, as close to the ...
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ADAU1328 Table 11. Pin Function Changes in TDM and AUX Modes Mnemonic Stereo Modes ASDATA1 ADC1 Data Out ASDATA2 ADC2 Data Out DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data In ALRCLK ADC ...
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ALRCLK ABCLK DSDATA1 DAC L1 DAC R1 (TDM_IN) 4-ON-CHIP ADC CHANNELS ASDATA1 ADC L1 ADC R1 (TDM_OUT) 32 BITS MSB DLRCLK LEFT (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ALRCLK ABCLK 4 ON-CHIP ADC CHANNELS AUXILIARY ...
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ADAU1328 ALRCLK ABCLK UNUSED SLOTS DSDATA1 EMPTY EMPTY EMPTY (TDM_IN) 4 ON-CHIP ADC CHANNELS ASDATA1 ADC L1 ADC R1 ADC L2 ADC R2 (TDM_OUT) DLRCLK (AUX PORT) DBCLK (AUX PORT) DSDATA2 MSB (AUX1_IN) DSDATA3 MSB (AUX2_IN) ASDATA2 MSB (AUX1_OUT) DSDATA4 ...
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DAISY-CHAIN MODE The ADAU1328 also allows a daisy-chain configuration to expand the system to 8 ADCs and 16 DACs (see Figure 18). In this mode, the DBCLK frequency is 512 f of the DAC TDM data stream belong to the ...
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ADAU1328 DLRCLK DBCLK 8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN DSDATA1 DAC L1 DAC R1 (IN) DSDATA2 (OUT) DSDATA3 DAC L3 DAC R3 (IN) DSDATA4 (OUT) 32 BITS MSB FIRST SECOND ADAU1328 ADAU1328 Figure 19. Dual-Line DAC ...
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ALRCLK ABCLK 4 ADC CHANNELS OF SECOND IC IN THE CHAIN ASDATA1 (TDM_OUT OF THE SECOND ADAU1328 ADC L1 ADC R1 ADC L2 ADC R2 ADC L1 ADC R1 ADC L2 ADC R2 IN THE CHAIN) ASDATA2 (TDM_IN OF THE ...
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ADAU1328 t DBH DBCLK t DBL t DLS DLRCLK t DDS DSDATA LEFT-JUSTIFIED MSB MODE t DDH DSDATA 2 I S-JUSTIFIED MODE DSDATA RIGHT-JUSTIFIED MODE t ABH ABCLK t ABL t ALS ALRCLK t ABDD ASDATA LEFT-JUSTIFIED MSB MODE ASDATA ...
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Table 12. Pin Function Changes in TDM and AUX Modes (Replication of Table 11) Mnemonic Stereo Modes ASDATA1 ADC1 Data Out ASDATA2 ADC2 Data Out DSDATA1 DAC1 Data In DSDATA2 DAC2 Data In DSDATA3 DAC3 Data In DSDATA4 DAC4 Data ...
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ADAU1328 CONTROL REGISTERS DEFINITIONS 2 C and SPI ports. The global address for the ADAU1328 is 0x04, shifted left 1 bit due to the R/ W bit. However, The format is the same for ADR0 ...
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Table 16. PLL and Clock Control 1 Bit Value Function 0 0 PLL clock 1 MCLK 1 0 PLL clock 1 MCLK 2 0 Enabled 1 Disabled 3 0 Not locked 1 Locked 7:4 0000 Reserved DAC CONTROL REGISTERS Table ...
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ADAU1328 Table 19. DAC Control 2 Bit Value Function 0 0 Unmute 1 Mute 2:1 00 Flat 01 48 kHz curve 10 44.1 kHz curve 11 32 kHz curve 4 Reserved ...
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ADC CONTROL REGISTERS Table 22. ADC Control 0 Bit Value Function 0 0 Normal 1 Power-down 1 0 Off Unmute 1 Mute 3 0 Unmute 1 Mute 4 0 Unmute 1 Mute 5 0 Unmute 1 ...
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ADAU1328 Table 24. ADC Control 2 Bit Value Function 0 0 50/50 (allows 32-/24-/20-/16-BCLK/channel) 1 Pulse (32-BCLK/channel Drive out on falling edge (DEF) 1 Drive out on rising edge 2 0 Left low 1 Left high 3 0 ...
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ADDITIONAL MODES The ADAU1328 offers several additional modes for board level design enhancements. To reduce the EMI in board level design, serial data can be transmitted without an explicit BCLK. See Figure 27 for an example of a DAC TDM ...
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ADAU1328 APPLICATION CIRCUITS Typical applications circuits are shown in Figure 29 through Figure 32. Figure 29 shows a typical ADC input filter circuit. Recommended loop filters for LR clock and master clock as the PLL reference are shown in Figure ...
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... OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range 1 ADAU1328BSTZ −40°C to +85°C 1 ADAU1328BSTZ-RL −40°C to +85°C EVAL-ADAU1328EB Pb-free part. 0.75 1.60 0.60 MAX 0.45 0.20 0.09 7° 3.5° 12 0° ...
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ADAU1328 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06102-0-6/06(0) Rev Page ...