CS4265-CNZ Cirrus Logic Inc, CS4265-CNZ Datasheet - Page 38

• Manufacturer Part Number: CS4265-CNZ
• Description: IC CODEC 24BIT 104DB 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS4265-CNZ

• Package / Case: 32-QFN
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 104 / 104
• Voltage - Supply, Analog: 3.13 V ~ 5.25 V
• Voltage - Supply, Digital: 3.13 V ~ 5.25 V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 4
• Number Of Dac Outputs: 2
• Conversion Rate: 192 KSPS
• Interface Type: Serial (I2S)
• Resolution: 24 bit
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 95 dB ADC / - 90 dB DAC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1001 - BOARD EVAL FOR CS4265 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1039

38
6.4.3
6.4.4
6.4.5
6.5
6.5.1
Reserved
7
MCLK Frequency - Address 05h
Mute ADC (Bit 2)
Function:
When this bit is set, the serial audio output of the both ADC channels is muted.
ADC High-Pass Filter Freeze (Bit 1)
Function:
When this bit is set, the internal high-pass filter is disabled.The current DC offset value will be frozen and
continue to be subtracted from the conversion result. See
page 25.
Master / Slave Mode (Bit 0)
Function:
This bit selects either master or slave operation for the serial audio port. Setting this bit selects Master
Mode, while clearing this bit selects Slave Mode.
Master Clock Dividers (Bits 6:4)
Function:
Sets the frequency of the supplied MCLK signal. See
ADC_DIF
0
1
MCLK
Freq2
6
MCLK Divider
Reserved
Reserved
Left-Justified, up to 24-bit data (default)
÷ 1.5
÷ 1
÷ 2
÷ 3
÷ 4
MCLK
Freq1
5
I²S, up to 24-bit data
Table 9. ADC Digital Interface Formats
Description
Table 10. MCLK Frequency
MCLK Freq2
MCLK
Freq0
4
0
0
0
0
1
1
1
Reserved
MCLK Freq1
3
Table 10
“High-Pass Filter and DC Offset Calibration” on
0
0
1
1
0
0
1
for the appropriate settings.
Reserved
Format
0
1
2
MCLK Freq0
0
1
0
1
0
1
x
Reserved
Figure
1
5
6
CS4265
Reserved
DS657F2
0