CY7C341B-25JC Cypress Semiconductor Corp, CY7C341B-25JC Datasheet - Page 5

• Manufacturer Part Number: CY7C341B-25JC
• Description: IC EPLD 192MACROCELL 25NS 84PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C341B-25JC

• Programmable Type: EPLD
• Number Of Macrocells: 192
• Voltage - Input: 5V
• Speed: 25ns
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Family Name: MAX®
• # Macrocells: 192
• Number Of Usable Gates: 3750
• Frequency (max): 62.5MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 12
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1261

External Switching Characteristics
Document #: 38-03016 Rev. *A
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
f
t
f
Notes:
Parameter
PD1
PD2
SU
CO1
H
WH
WL
MAX
ACO1
AS1
AH
AWH
AWL
CNT
ODH
CNT
ACNT
ACNT
4.
5.
6.
3.
C1 = 35 pF.
The f
This parameter is measured with a positive-edge-triggered clock at the register. For negative-edge clocking, the t
This parameter is measured with a 16-bit counter programmed into each LAB.
MAX
values represent the highest frequency for pipeline data.
Dedicated Input to Combinatorial Output
Delay
I/O Input to Combinatorial Output Delay
Global Clock Set-up Time
Synchronous Clock Input to Output Delay
Input Hold Time from Synchronous Clock
Input
Synchronous Clock Input High Time
Synchronous Clock Input Low Time
Maximum Register Toggle Frequency
Dedicated Asynchronous Clock Input to
Output Delay
Dedicated Input or Feedback Set-up Time to
Asynchronous Clock Input
Input Hold Time from Asynchronous Clock
Input
Asynchronous Clock Input HIGH Time
Asynchronous Clock Input LOW Time
Minimum Global Clock Period
Output Data Hold Time After Clock
Maximum Internal Global Clock Frequency
Minimum Internal Array Clock Frequency
Maximum Internal Array Clock Frequency
[3]
[3]
Description
Over the Operating Range
[4]
[5]
[5]
[3]
[3]
[6]
[6]
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Min.
62.5
15
50
50
11
7C341B-25
0
8
8
5
6
9
2
Max
ACH
25
40
14
25
20
20
and t
ACL
Min.
12.5
12.5
40.0
33.3
33.3
parameter must be swapped.
25
10
10
16
14
7C341B-35
0
2
CY7C341B
Max
35
55
20
35
30
30
Page 5 of 11
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns