CY7C341B-25JC Cypress Semiconductor Corp, CY7C341B-25JC Datasheet - Page 2

• Manufacturer Part Number: CY7C341B-25JC
• Description: IC EPLD 192MACROCELL 25NS 84PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C341B-25JC

• Programmable Type: EPLD
• Number Of Macrocells: 192
• Voltage - Input: 5V
• Speed: 25ns
• Mounting Type: Surface Mount
• Package / Case: 84-PLCC
• Family Name: MAX®
• # Macrocells: 192
• Number Of Usable Gates: 3750
• Frequency (max): 62.5MHz
• Propagation Delay Time: 25ns
• Number Of Logic Blocks/elements: 12
• # I/os (max): 64
• Operating Supply Voltage (typ): 5V
• In System Programmable: No
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 84
• Package Type: PLCC
• Memory Type: EPROM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1261

Design Security
The CY7C341B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the device.
The CY7C341B is fully functionally tested and guaranteed through
complete testing of each programmable EPROM bit and all internal
logic elements thus ensuring 100% programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Document #: 38-03016 Rev. *A
Logic Block Diagram
18, 19, 39, 40, 60, 61, 81, 82 (E1, E2, K5, L5, G10, G11, A7, B7)
4
5
6
7
8
9
10 (A1)
11 (B2)
12 (C2)
13 (B1)
14 (C1)
15 (D2)
16 (D1)
17 (E3)
20
21
22 (G3)
23 (G1)
25
26 (H1)
27 (H2)
28
29 (K1)
30
31
32 (K2)
33 (K3)
34
35
36 (K4)
37
38
1 (A6)
2 (A5)
41 (K6)
42 (J6)
(C5)
(A4)
(B4)
(A3)
(A2)
(B3)
(F2)
(F3)
(F1)
(J1)
(J2)
(L1)
(L2)
(L3)
(L4)
(J5)
INPUT/CLK
INPUT
INPUT
INPUT
MACROCELL 53–64
MACROCELL 89–96
MACROCELL 21–32
MACROCELL 37–48
MACROCELL 69–80
MACROCELL 9–16
LAB A
LAB B
LAB C
LAB D
LAB E
LAB F
MACROCELL81
MACROCELL82
MACROCELL83
MACROCELL84
MACROCELL85
MACROCELL86
MACROCELL87
MACROCELL88
MACROCELL1
MACROCELL2
MACROCELL3
MACROCELL4
MACROCELL5
MACROCELL6
MACROCELL7
MACROCELL8
MACROCELL17
MACROCELL18
MACROCELL19
MACROCELL20
MACROCELL33
MACROCELL34
MACROCELL35
MACROCELL36
MACROCELL49
MACROCELL50
MACROCELL51
MACROCELL52
MACROCELL65
MACROCELL66
MACROCELL67
MACROCELL68
3, 24, 45, 66 (B5, G2, K7, E10)
SYSTEMCLOCK
P
A
V
GND
I
CC
250
200
150
100
() – PERTAIN TO 84-PIN PGA PACKAGE
50
MACROCELL 117–128
MACROCELL 133–144
MACROCELL 149–160
MACROCELL 165–176
MACROCELL 185–192
MACROCELL 105–112
MACROCELL 100
MACROCELL 101
MACROCELL 102
MACROCELL 103
MACROCELL 104
MACROCELL 113
MACROCELL 114
MACROCELL 115
MACROCELL 116
MACROCELL 129
MACROCELL 130
MACROCELL 131
MACROCELL 132
MACROCELL 145
MACROCELL 146
MACROCELL 147
MACROCELL 148
MACROCELL 161
MACROCELL 162
MACROCELL 163
MACROCELL 164
MACROCELL 177
MACROCELL 178
MACROCELL 179
MACROCELL 180
MACROCELL 181
MACROCELL 182
MACROCELL 183
MACROCELL 184
MACROCELL97
MACROCELL98
MACROCELL99
0
Output Drive Current
V
LAB G
LAB H
LAB I
LAB J
LAB K
LAB L
1
O
INPUT
INPUT
INPUT
INPUT
OUTPUT VOLTAGE (V)
I
OL
2
(C6) 84
(C7) 83
(L7) 44
(J7) 43
46 (L6)
47 (L8)
48 (K8)
49 (L9)
50 (L10)
51 (K9)
52 (L11)
53 (K10)
54 (J10)
55 (K11)
56 (J11)
57 (H10)
58 (H11)
59 (F10)
62 (G9)
63 (F9)
64 (F11)
65 (E11)
67 (E9)
68 (D11)
69 (D10)
70 (C11)
71 (B11)
72 (C10)
73 (A11)
74 (B10)
75 (B9)
76 (A10)
77 (A9)
78 (B8)
79 (A8)
80 (B6)
V
Room Temp.
I
CC
3
OH
= 5.0V
4
CY7C341B
5
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