CY7C341B-25JC Cypress Semiconductor Corp, CY7C341B-25JC Datasheet
CY7C341B-25JC
Specifications of CY7C341B-25JC
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CY7C341B-25JC Summary of contents
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... LAB. Each LAB is interconnected with a programmable interconnect array, allowing all signals to be routed throughout the chip. The speed and density of the CY7C341B allows used in a wide range of applications, from replacement of large amounts of 7400-series TTL logic, to complex controllers and multifunction chips ...
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... The bit that controls this function, along with all other program data, may be reset simply by erasing the device. The CY7C341B is fully functionally tested and guaranteed through complete testing of each programmable EPROM bit and all internal logic elements thus ensuring 100% programming yield. ...
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... RSU DELAY LAD SYSTEM CLOCK DELAY t ICS CLOCK DELAY t IC LOGIC ARRAY DELAY t FD I/O DELAY t IO Figure 1. CY7C341B Internal Timing Model CY7C341B PGA Bottom View I/O I/O GND I/O INPUT I/O I/O I/O GND INPUT V I/O CC I/O INPUT INPUT I/O ...
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... CC OL GND GND O CC Test Conditions 1.0 MHz 0V 1.0 MHz OUT R1 464 250 (b) C341B-7 1.75V parameter refers to low-level TTL output current. OL CY7C341B [ +25 mA [1] 2.0V to +7.0V Ambient Temperature + – + 10% Min. Max. 4.75(4.5) 5.25(5.5) [2] 2.4 [2] 0.45 2 0.3 CC 0.3 0.8 10 +10 40 +40 100 100 Max ...
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... This parameter is measured with a 16-bit counter programmed into each LAB. Document #: 38-03016 Rev. *A Over the Operating Range Description Commercial [3] Commercial Commercial [3] Commercial Commercial Commercial Commercial [4] Commercial Commercial Commercial Commercial [5] Commercial [5] Commercial Commercial Commercial [6] Commercial Commercial [6] Commercial CY7C341B 7C341B-25 7C341B-35 Min. Max Min. Max 12.5 8 12.5 62.5 40 ...
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... CLR t Programmable Interconnect Array Delay Commercial PIA Note pF. Document #: 38-03016 Rev. *A Over the Operating Range Description Commercial Commercial Commercial Commercial Commercial [3] Commercial [3] Commercial [7] Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial CY7C341B 7C341B-25 7C341B-35 Min. Max Min. Max ...
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... DEDICATED INPUTS OR REGISTERED FEEDBACK ASYNCHRONOUS CLOCK INPUT Internal Combinatorial INPUT PIN I/O PIN EXPANDER ARRAY DELAY LOGIC ARRAY INPUT LOGIC ARRAY OUTPUT OUTPUT PIN Document #: 38-03016 Rev PD1 PD2 CO1 AS1 EXP CY7C341B t t AWH AWL LAC LAD t t COMB OD Page ...
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... SYSTEM CL OCK PIN t IN SYSTEM CLOCK AT REGISTER t RSU DATA FROM LOGIC ARRAY Internal Synchronous CLOCK FROM LOGIC ARRAY t RD DATA FROM LOGIC ARRAY OUTPUT PIN Ordering Information Speed (ns) Ordering Code 25 CY7C341B-25HC/HI CY7C341B-25JC/JI CY7C341B-25RC/RI 35 CY7C341B-35HC/HI CY7C341B-35JC/JI CY7C341B-35RC/RI Document #: 38-03016 Rev AWL RSU LATCH FD t ...
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... Package Diagrams Document #: 38-03016 Rev. *A 84-Leaded Windowed Leaded Chip Carrier H84 CY7C341B 51-80081 Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 84-Lead Windowed Pin Grid Array R84 CY7C341B 51-85006-A 51-80026-*B ...
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... Document Title: CY7C341B 192-Macrocell MAX Document Number: 38-03016 Issue REV. ECN NO. Date ** 106316 05/17/01 *A 113613 04/11/02 Document #: 38-03016 Rev. *A ® EPLD Orig. of Change SZV Change from ecn #: 38-00137 to 38-03016 OOR PGA package diagram dimensions were updated CY7C341B Description of Change Page ...