MMA8110EG Freescale Semiconductor, MMA8110EG Datasheet - Page 29

• Manufacturer Part Number: MMA8110EG
• Description: Board Mount Accelerometers Z-AXIS 100G W/CAP BOND
• Manufacturer: Freescale Semiconductor
• Series: MMA81r

Specifications of MMA8110EG

• Sensing Axis: Z
• Acceleration: 100 g
• Sensitivity: 4.01 mV/g
• Package / Case: SOIC-20 Wide
• Axis: Z
• Acceleration Range: ±100g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Sensors
Freescale Semiconductor
If self-test locking has been activated, the ST bit will be cleared in the response from the device. Self-Test locking is described in
Section
4.6.8
The reverse initialization command conforms to the description provided in Section 6.2.1 of the DSI Bus Standard, Version 2.0.
At power-up the device is fully compliant with the DSI 1.1 protocol. The initialization command must be transmitted as a DSI 1.1
compliant long command structure. Features of the DSI 2.0 protocol can not be accessed until a valid DSI 1.1 compliant initial-
ization sequence is performed and the enhanced mode format registers are properly configured.
Figure 4-1
of a DSI Reverse Initialization command. Reverse Initialization commands are recognized only at BUSOUT. The BUSIN node is
tested for a bus short to battery high voltage condition, and the bus fault (BF) flag set if an error condition is detected. If no bus
fault condition is detected and the BS bit is set in the command structure, the bus switch will be closed.
If the device has been pre-programmed, PA3 - PA0 and A3 - A0 must match the pre-programmed address. If no device address
has been previously programmed into the OTP array, PA3 - PA0 contain the device address, while A3 - A0 must be zero. If any
addressing condition is not met, the device address is not assigned, the bus switch will remain open and the device will not re-
spond to the Reverse Initialization command. If the BS bit is set, the DSI bus voltage level is disregarded for approximately
180 μs following reverse initialization to allow hold capacitors on downstream slaves to charge.
In the response, bits D15 - D12 and D3 - D0 will contain the device address. If the device was unprogrammed when the reverse
initialization command was issued, the device address is assigned as the command executes. Both fields will contain the value
PA3 - PA0 to indicate successful device address assignment.
Initialization or reverse initialization commands which attempt to assign device address zero are ignored.
D15
D15
NV
A3
A3
D7
Response
Length
10
11
12
13
14
15
8
9
4.6.6.
D14
D14
A2
A2
D6
BS
Reverse Initialization Command
illustrates the sequence of operations performed following negation of internal power-on reset (POR) and execution
D13
D13
D5
A1
A1
B1
D14
0
Table 4-26 Short Response Structure - Enable Self-Test Stimulus Command
D12
Table 4-27 Long Response Structure - Enable Self-Test Stimulus Command
D12
A0
A0
D4
B0
Table 4-29 Long Response Structure - Reverse Initialization Command
Data
D11
PA3
D11
D3
0
0
D13
Table 4-28 Reverse Initialization Command Structure
0
D10
D10
PA2
D2
0
0
PA1
D9
D9
D1
0
D12
0
0
PA0
D8
D0
D8
BF
D11
0
0
Data
Data
D10
NV
D7
NV
D7
A3
A3
0
D9
0
D6
A2
A2
D6
BS
Response
U
Address
D8
0
D5
ST
A1
D5
A1
B1
NV
D7
BS
D4
A0
A0
D4
B0
D6
U
AT1
D3
C3
D3
A3
1
ST
D5
AT0
D2
Command
C2
D2
A2
1
BS
D4
D1
C1
D1
A1
S
1
AT1 AT0
D3
GF
D0
C0
D0
A0
1
D2
MMA81XXEG
0 to 8 bits
D1
S
4 bits
CRC
CRC
4 bits
CRC
GF
D0
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