MMA8110EG Freescale Semiconductor, MMA8110EG Datasheet - Page 10

• Manufacturer Part Number: MMA8110EG
• Description: Board Mount Accelerometers Z-AXIS 100G W/CAP BOND
• Manufacturer: Freescale Semiconductor
• Series: MMA81r

Specifications of MMA8110EG

• Sensing Axis: Z
• Acceleration: 100 g
• Sensitivity: 4.01 mV/g
• Package / Case: SOIC-20 Wide
• Axis: Z
• Acceleration Range: ±100g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

SECTION 3 OTP MEMORY
MMA81XXEG/MMA82XXEG/MMA82XXTEG family features One-Time-Programmable (OTP) memory implemented via a fuse
array. OTP is organized as an array of 96 bits which contains the trim data, configuration data, and serial number for each device.
Sixteen bits of the OTP array may be programmed by the customer through the DSI Bus.
3.1
Contents of OTP memory are transferred to a set of registers following power-on reset, after which the OTP array is powered-
down. Contents of the register array are static and may be read at any time following the transfer of data from the OTP memory.
Write operations to OTP mirror registers are supported when the device is in test mode, however any data stored in the register
will be lost when the device is powered down. The mirror registers are also restored when an OTP read operation is performed.
In addition to the registers which mirror OTP memory contents, several other registers are provided. Among these are the OTP
Control Registers which controls OTP programming operations and may be used to restore the registers from the OTP memory.
3.2
Customer-accessible OTP bits are shown in
DEVCFG2 and registers REG-8 through REG-F are programmed by the customer. Other bits are programmed and locked during
manufacturing. There is no requirement to program any bits in DEVCFG1 or DEVCFG2 for the device to be fully operational.
MMA81XXEG
10
Address
$0A
$0B
$0C
$0D
$0E
$00
$01
$02
$03
$04
$05
$06
$07
$08
$09
$0F
INTERNAL REGISTER ARRAY AND OTP MEMORY
OTP WORD ASSIGNMENT
Location
RESERVED
DEVCFG1
DEVCFG2
V
Register
REG-C
REG-D
REG-8
REG-9
REG-A
REG-B
REG-E
REG-F
PP
TYPE
SN0
SN1
SN2
SN3
/TEST
D
CLK
OUT
D
IN
ORDER
LOCK2
S15
S23
S31
S7
7
0
PERIPHERAL
Table 3-1 Customer Accessible Data
INTERFACE
Figure 3-1. OTP Interface Overview
Table
PAR2
S14
S22
S30
SERIAL
S6
6
0
0
3-1. Unprogrammed OTP bits are read as logic ‘0’ values. DEVCFG1,
Customer Defined
GLDE
AXIS
S13
S21
S29
S5
5
0
DDIS
Customer Defined
Customer Defined
Customer Defined
Customer Defined
Customer Defined
Customer Defined
Customer Defined
Customer Defined
S12
S20
S28
REGISTER
S4
4
0
0
Bit Function
ARRAY
ARRAY
OTP
AD3
S11
S19
S27
S3
3
0
0
RNG2
AD2
S18
S26
S10
S2
TO DIGITAL
INTERFACE
2
0
Freescale Semiconductor
RNG1
AD1
S17
S25
AT1
S1
S9
1
0
RNG0
Sensors
AD0
S16
S24
AT0
S0
S8
0
0