MMA8110EG Freescale Semiconductor, MMA8110EG Datasheet - Page 18

• Manufacturer Part Number: MMA8110EG
• Description: Board Mount Accelerometers Z-AXIS 100G W/CAP BOND
• Manufacturer: Freescale Semiconductor
• Series: MMA81r

Specifications of MMA8110EG

• Sensing Axis: Z
• Acceleration: 100 g
• Sensitivity: 4.01 mV/g
• Package / Case: SOIC-20 Wide
• Axis: Z
• Acceleration Range: ±100g
• Voltage - Supply: 6.3 V ~ 30 V
• Output Type: Digital
• Bandwidth: -
• Interface: SPI
• Mounting Type: Surface Mount
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.5.1.9
Ground Fault Flag (GF)
If ground loss detection has been enabled and a ground fault condition is detected, this bit will be set in the response to Request
Status, Read Acceleration Data, Disable Self-Test Stimulus or Activate Self-Test Stimulus commands. If ground loss detection is
not enabled, this bit will always be read as a logic ‘0’ value.
1 - Ground fault condition detected
0 - Ground connection within specified limits, or ground loss detection disabled.
4.5.1.10 Nonvolatile Memory Program Control Bit (NV)
This bit enables programming of customer-programmed OTP locations when set during an Initialization or Reverse Initialization
command. Data to be programmed are transferred to the device during subsequent Read Write NVM commands.
1 - Enable OTP programming
0 - OTP programming circuitry disabled
4.5.1.11 Assigned Device Address (PA3 - PA0)
This field contains the device address to be assigned during an Initialization or Reverse Initialization command. The address
assigned is reported by the device in response to the Initialization or Reverse Initialization command.
4.5.1.12 Register Address (RA3 - RA0)
This field determines the register associated with a Read Write NVM or Read Register Data command. The two Bank Select bits
(B1, B0) are used to additionally specify a nibble or bit when a Read Write NVM command is executed.
4.5.1.13 Register Data (RD7 - RD0)
RD3 - RD0 contain data to be written to an OTP location when a Read Write NVM command is executed if the NV bit is set. RD3
- RD0 contain the data read from the selected register in response to a Read Write NVM command if the NV bit is cleared. RD7
- RD0 indicate the contents of the selected register in response to a Read Register Data command.
4.5.1.14 Format Control Register Read/Write Bit (R/W)
This bit controls the operation performed by a Format Control command.
1 - Write Format Control register selected by FA2 - FA0
0 - Read Format Control register unless global command
4.5.1.15 Accelerometer Status Flag (S)
This bit provides a cumulative indication of the various error conditions which are monitored by the device.
1 - Either one or more error conditions have been detected and/or the internal Self-Test stimulus circuitry is active
0 - No error condition has been detected
The following conditions will cause the status flag to be set:
*Internal Self-Test stimulus circuitry is active
OTP array parity fault
OTP fuse threshold fault (partially-programmed fuse)
Transient undervoltage condition
Ground fault (if GLDE bit in DEVCFG2 is set)
4.5.1.16 Self-Test State (ST)
This bit indicates whether internal self-test stimulus circuitry is active in response to Request Status, Disable Self-Test Stimulus
and Activate Self-Test Stimulus commands.
1 - Self-Test stimulus active
0 - Self-Test stimulus disabled
4.5.1.17 Undervoltage Flag (U)
This flag is set if the voltage at HCAP is below a specified threshold. Refer to
Section 1.3.1
and
Section 5
for further details.
MMA81XXEG
Sensors
18
Freescale Semiconductor