MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 98
MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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Bus Operation
4.3 DATA TRANSFER CYCLES
The transfer of data between the QUICC and other devices involves the following signals:
The address and data buses are both parallel, nonmultiplexed buses. The bus master
moves data on the bus by issuing control signals, and the bus uses a handshake protocol
to ensure correct movement of the data. In all bus cycles, the bus master is responsible for
deskewing all signals it issues at both the start and end of the cycle. In addition, the bus mas-
ter is responsible for deskewing the acknowledge and data signals from the slave devices.
The following paragraphs define read, write, and read-modify-write cycle operations. Each
bus cycle is defined as a succession of states that apply to the bus operation. These states
are different from the QUICC states described for the CPU32+. The clock cycles used in the
descriptions and timing diagrams of data transfer cycles are independent of the clock fre-
quency. Bus operations are described in terms of external bus states.
4-22
• Address Bus A31–A0
• Data Bus D31–D0
• Control Signals
When using the fast termination option (cycle length is two
clocks), DS is asserted only in a read cycle, not in a write cycle.
DSACKx is only internally asserted for fast termination cycles.
*
DSACKx
D31–D0
DSACKx only internally asserted for fast termination cycles.
CLKO1
R/W
AS
DS
S0
Freescale Semiconductor, Inc.
Figure 4-14. Fast Termination Timing
S1
For More Information On This Product,
TWO WAIT STATES IN READ
S2
S3
MC68360 USER’S MANUAL
SW
Go to: www.freescale.com
SW
*
SW
NOTES
SW
*
S4
S5
S0
TERMINATION
S1
READ
FAST
S4
S5
S0
TERMINATION
S1
WRITE
FAST
S4
S5
S0
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