MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 372
MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68360EM25VL
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68360EM25VL
Manufacturer:
MOTOROLA/摩托罗拉
Quantity:
20 000
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IDMA Channels
IDMA channel 1 initialization required for this example:
7.6.4.6.2 Single Address Mode (Flyby Transfers). Each IDMA channel can be indepen-
dently programmed to provide single address transfers. Figure 7-14 illustrates a transfer
from memory to a peripheral. The DHR is not used by the IDMA, since the transfer occurs
directly from a device to memory. This mode is often referred to as "flyby" mode because
the DHR is not used.
7-48
• ICCR = $0720. Recommended normal configuration.
• FCR1 = $89. Source function code is 1000; destination function code is 1001.
• SAPR1 = $00000002. Source address.
• DAPR1 = $20000002. Destination address.
• BCR1 = $00000008. Byte transfer count.
• CSR1 = $FF. Clear any CSR bits that are currently set.
• CMAR1 = $00. Disable interrupts for this example.
• CMR1 = $4711. Internal maximum transfer rate; starts IDMA.
Bus Access #
10
11
1
2
3
4
5
6
7
8
9
Figure 7-14. Single Address Transfer Example
Freescale Semiconductor, Inc.
QUICC
Address (Hex)
IDMA
For More Information On This Product,
$00000002
$20000002
$20000003
$00000004
$20000004
$20000005
$20000006
$20000007
$00000008
$20000008
$20000009
MC68360 USER’S MANUAL
Go to: www.freescale.com
ADDR.
DACKx
JUST ONE BUS CYCLE
REQUIRED
Operation
DATA
BUS
Read
Write
Write
Read
Write
Write
Write
Write
Read
Write
Write
1
1
No. Bytes
2
1
1
4
1
1
1
1
2
1
1
PERIPHERAL
MEMORY
No. Bytes in DHR
2
1
0
4
3
2
1
0
2
1
0
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