MC68360EM25VL Freescale Semiconductor, MC68360EM25VL Datasheet - Page 424
MC68360EM25VL
Manufacturer Part Number
MC68360EM25VL
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360EM25VL
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
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Serial Interface with Time Slot Assigner
7.8.8 Serial Interface Synchronization
On rev A and B of the QUICC, the SI would reset itself if an unexpected sync pulse was seen
during the middle of a time frame. This would cause the SI to sync again on the following
sync pulse but it would also lead to an unresolved loss of synchronization of an SCC or SMC
operating in transparent or GCI modes (assuming that SCC or SMC was receiving data from
the SI).
In revision C.1 and later of the QUICC, the SI will ignore this unexpected sync pulse and
synchronize on the next sync pulse (it will not reset itself). This may lead to a reception of
one or two “bad” slots but the SCC or SMC will remain synchronized.
7.8.9 NMSI Configuration
The SI supports an NMSI mode for each of the SCCs and SMCs. The decision of whether
to connect a given SCC to the NMSI is made in the SICR. The decision of whether to con-
nect a given SMC to the NMSI is made in the SIMODE register.
An SCC or SMC may be connected to the NMSI, regardless of which other channels are
connected to a TDM channel. The user should note, however, that NMSI pins may be mul-
tiplexed with other functions at the parallel I/O lines. Therefore, if a combination of TDM and
NMSI channels is used, the decision of which SCCs and SMCs to connect and where to con-
nect them should be made consulting the QUICC pinout. Generally speaking, the TDMa
channel is multiplexed with many of the SCC4 pins; whereas, the TDMb channel is multi-
plexed with many of the SCC3 pins.
The clocks that are provided to the SCCs and SMCs are derived from twelve sources: four
internal baud rate generators and eight external CLK pins (see Figure 7-35). There are two
main advantages to the bank-of-clocks approach. First, an SCC or SMC is not forced to
7-100
7. If the 1 GCI data clock is required, set PBPAR bit 11 and PBDIR bit 11, which
8. PCPAR bit 11 = 1. Configures L1RSYNCa.
9. SIGMR = $04. Enable TDMa (one static TDM).
10. 1SICMR is not used.
11. 1SISTR and SIRP do not need to be read, but can be used for debugging
12. 1Enable the SCC1 for HDLC operation (to handle the LAPD protocol of
configures L1CLKOa as an output.
information once the channels are enabled.
the D channel), set SCC2 and SCC4 as desired, and enable SMC1 for SCIT
operation.
Rev A mask is C63T
Rev B mask are C69T, and F35G
Current Rev C mask are E63C, E68C and F15W
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
NOTE
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