A80386DX33 Intel, A80386DX33 Datasheet - Page 95

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

6 INSTRUCTION SET
This section describes the Intel386 DX instruction
set A table lists all instructions along with instruction
encoding diagrams and clock counts Further details
of the instruction encoding are then provided in the
following sections which completely describe the
encoding structure and the definition of all fields oc-
curring within Intel386 DX instructions
6 1 Intel386
To calculate elapsed time for an instruction multiply
the instruction clock count as listed in Table 6-1
below by the processor clock period (e g 50 ns for
a 20 MHz Intel386 DX 40 ns for a 25 MHz Intel386
DX and 30 ns for a 33 MHz Intel386 DX)
For more detailed information on the encodings of
instructions refer to section 6 2 Instruction Encod-
ings Section 6 2 explains the general structure of
instruction encodings and defines exactly the en-
codings of all fields contained within the instruction
Instruction Clock Count Assumptions
1 The instruction has been prefetched decoded
and is ready for execution
ENCODING AND CLOCK COUNT
SUMMARY
TM
DX INSTRUCTION
2 Bus cycles do not require wait states
3 There are no local bus HOLD requests delaying
4 No exceptions are detected during instruction ex-
5 If an effective address is calculated it does not
Instruction Clock Count Notation
1 If two clock counts are given the smaller refers to
2 n
3 m
Wait States
Add 1 clock per wait state to instruction execution
for each data access
processor access to the bus
ecution
use two general register components One regis-
ter scaling and displacement can be used within
the clock counts shown However if the effective
address calculation uses two general register
components add 1 clock to the clock count
shown
a register operand and the larger refers to a mem-
ory operand
tion executed where the entire displacement (if
any) counts as one component the entire imme-
diate data (if any) counts as one component and
each of the other bytes of the instruction and pre-
fix(es) each count as one component
e
e
number of times repeated
number of components in the next instruc-
Intel386
TM
DX MICROPROCESSOR
95