A80386DX33 Intel, A80386DX33 Datasheet - Page 125

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A80386DX33

Manufacturer Part Number
A80386DX33
Description
IC MPU 32-BIT 5V 33MHZ 132-PGA
Manufacturer
Intel
Datasheet

Specifications of A80386DX33

Processor Type
386DX
Features
32-bit
Speed
33MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-PGA
Family Name
Intel386 DX
Device Core Size
32b
Frequency (max)
33MHz
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
132
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
807129

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
A80386DX33
Manufacturer:
INTEL
Quantity:
569
9 5 A C SPECIFICATIONS
9 5 1 A C Spec Definitions
The A C specifications given in Tables 9-4 9-5 and
9-6 consist of output delays input setup require-
ments and input hold requirements All A C specifi-
cations are relative to the CLK2 rising edge crossing
the 2 0V level
A C spec measurement is defined by Figure 9-1 In-
puts must be driven to the voltage levels indicated
by Figure 9-1 when A C specifications are mea-
sured Intel386 DX output delays are specified with
minimum and maximum limits measured as shown
The minimum Intel386 DX delay times are hold times
NOTES
1 Input waveforms have tr
2 See section 9 5 8 for typical output rise time versus load capacitance
Figure 9-1 Drive Levels and Measurement Points for A C Specifications
s
2 0 ns from 0 8V to 2 0V
provided to external circuitry Intel386 DX input set-
up and hold times are specified as minimums defin-
ing the smallest acceptable sampling window Within
the sampling window a synchronous input signal
must be stable for correct Intel386 DX operation
Outputs NA
BE0 – BE3
the beginning of phase one D0 – D31 (write cycles)
only change at the beginning of phase two The
READY
D0 – D31 (read cycles) inputs are sampled at the be-
ginning of phase one The NA
NMI inputs are sampled at the beginning of phase
two
Intel386
HOLD BUSY
A2 – A31 and HLDA only change at
W R
TM
DX MICROPROCESSOR
D C
ERROR
BS16
M IO
PEREQ and
231630 –37
INTR and
LOCK
125

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