A80386DX33 Intel, A80386DX33 Datasheet - Page 81

• Manufacturer Part Number: A80386DX33
• Description: IC MPU 32-BIT 5V 33MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX33

• Processor Type: 386DX
• Features: 32-bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 33MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807129

5 4 3 4 PIPELINED ADDRESS
Address pipelining is the option of requesting the
address and the bus cycle definition of the next in-
ternally pending bus cycle before the current bus
cycle is acknowledged with READY
ADS
address is issued The address pipelining option is
controlled on a cycle-by-cycle basis with the NA
input signal
Once a bus cycle is in progress and the current ad-
dress has been valid for at least one entire bus
state the NA
phase one until the bus cycle is acknowledged Dur-
ing non-pipelined bus cycles therefore NA
sampled at the end of phase one in every T2 An
example is Cycle 2 in Figure 5-16 during which NA
is sampled at the end of phase one of every T2 (it
was asserted once during the first T2 and has no
further effect during that bus cycle)
Following any idle bus state (Ti) addresses are non-pipelined Within non-pipelined bus cycles NA
Therefore to begin address pipelining during a group of non-pipelined bus cycles requires a non-pipelined cycle with at least one wait state
(Cycle 2 above)
is asserted by the Intel386 DX when the next
Figure 5-16 Transitioning to Pipelined Address During Burst of Bus Cycles
input is sampled at the end of every
asserted
is
If NA
to drive the address and bus cycle definition of the
next bus cycle and assert ADS
a bus request internally pending It may drive the
next address as early as the next bus state whether
the current bus cycle is acknowledged at that time or
not
Regarding the details of address pipelining the In-
tel386 DX has the following characteristics
1) For NA
be negated at that sampling window (see Figure
5-16 Cycles 2 through 4 and Figure 5-17 Cycles 1
through 4) If NA
asserted during the last T2 period of a bus cycle
BS16
are asserted the current bus size is taken to be
16 bits and the next address is not pipelined
is sampled asserted the Intel386 DX is free
Intel386
asserted has priority Therefore if both
to be sampled asserted BS16
TM
and BS16
is only sampled during wait states
DX MICROPROCESSOR
are both sampled
as soon as it has
231630 –20
must
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