MC68020RC33E Freescale Semiconductor, MC68020RC33E Datasheet - Page 79

• Manufacturer Part Number: MC68020RC33E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33.33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

State 4
State 5
5-32
MC68020/EC020—At the end of state 4 (S4), the processor latches the incoming data.
MC68020—The processor negates AS, DS, and DBEN during state 5 (S5). It holds the
MC68EC020—The processor negates AS and DS during state S5. It holds the address
address valid during S5 to provide address hold time for memory systems. R/W, SIZ1–
SIZ0, and FC2–FC0 also remain valid throughout S5.
The external device keeps its data and DSACK1/DSACK0 signals asserted until it
detects the negation of AS or DS (whichever it detects first). The device must remove
its data and negate DSACK1/DSACK0 within approximately one clock period after
sensing the negation of AS or DS. DSACK1/DSACK0 signals that remain asserted
beyond this limit may be prematurely detected for the next bus cycle.
valid during S5 to provide address hold time for memory systems. R/W , SIZ1, SIZ0,
and FC2–FC0 also remain valid throughout S5.
The external device keeps its data and DSACK1/DSACK0 signals asserted until it
detects the negation of AS or DS (whichever it detects first). The device must remove
its data and negate DSACK1/DSACK0 within approximately one clock period after
sensing the negation of AS or DS. DSACK1/DSACK0 signals that remain asserted
beyond this limit may be prematurely detected for the next bus cycle.
Freescale Semiconductor, Inc.
For More Information On This Product,
M68020 USER’S MANUAL
Go to: www.freescale.com
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