MC68020RC33E Freescale Semiconductor, MC68020RC33E Datasheet - Page 161

• Manufacturer Part Number: MC68020RC33E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33.33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

restore categories, the coprocessor uses the set of coprocessor format codes defined for
the M68000 coprocessor interface to indicate its status to the main processor.
7.2.1 Coprocessor General Instructions
The coprocessor general instruction category contains data processing instructions and
other general-purpose instructions for a given coprocessor.
7.2.1.1 FORMAT. Figure 7-6 shows the format of a coprocessor general instruction.
The mnemonic cpGEN is a generic mnemonic used in this discussion for all general
instructions. The mnemonic of a specific general instruction usually suggests the type of
operation it performs and the coprocessor to which it applies. The actual mnemonic and
syntax used to represent a coprocessor instruction is determined by the syntax of the
assembler or compiler that generates the object code.
A coprocessor general instruction consists of at least two words. The first word of the
instruction is an F-line operation code (bits 15–12 = 1111). The CpID field of the F-line
operation code is used during the coprocessor access to indicate which coprocessor in
the system executes the instruction. During accesses to the CIRs (refer to 7.1.4.2
Processor-Coprocessor Interface), the processor places the CpID on address lines
A15–A13.
Bits 8–6 = 000 of the first word of an instruction indicate that the instruction is in the
general instruction category. Bits 5–0 of the F-line operation code sometimes encode a
standard M68000 effective address specifier (refer to M68000PM/AD, M68000 Family
Programmer’s Reference Manual ). During the execution of a cpGEN instruction, the
coprocessor can use a coprocessor response primitive to request that the
MC68020/EC020 perform an effective address calculation necessary for that instruction.
Using the effective address specifier field of the F-line operation code, the processor then
determines the effective addressing mode. If a coprocessor never requests effective
address calculation, bits 5–0 can have any value (don't cares).
The second word of the general type instruction is the coprocessor command word. The
main processor writes this command word to the command CIR to initiate execution of the
instruction by the coprocessor.
An instruction in the coprocessor general instruction category optionally includes a
number of extension words following the coprocessor command word. These words can
provide additional information required for the coprocessor instruction. For example, if
7-8
15
1
Figure 7-6. Coprocessor General Instruction Format (cpGEN)
14
1
13
1
OPTIONAL EFFECTIVE ADDRESS OR COPROCESSOR-DEFINED EXTENSION WORDS
12
1
Freescale Semiconductor, Inc.
For More Information On This Product,
11
CpID
M68020 USER’S MANUAL
Go to: www.freescale.com
COPROCESSOR COMMAND
9
0
8
0
7
6
0
5
EFFECTIVE ADDRESS
MOTOROLA
0