MC68020RC33E Freescale Semiconductor, MC68020RC33E Datasheet - Page 193

• Manufacturer Part Number: MC68020RC33E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33.33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The take address and transfer data primitive described in 7.4.11 Take Address and
Transfer Data Primitive does not replace the effective address value that has been
calculated by the MC68020/EC020. The address that the main processor obtains in
response to the take address and transfer data primitive is not available to the write to
previously evaluated effective address primitive.
A coprocessor can issue an evaluate effective address and transfer data primitive followed
by this primitive to perform a read-modify-write operation that is not indivisible. The bus
cycles for this operation are normal bus cycles that can be interrupted, and the bus can be
arbitrated between the cycles.
7.4.11 Take Address and Transfer Data Primitive
The take address and transfer data primitive transfers an operand between the
coprocessor and an address supplied by the coprocessor. This primitive applies to general
and conditional category instructions. Figure 7-31 shows the format of the take address
and transfer data primitive.
The take address and transfer data primitive uses the CA, PC, and DR bits as described
in 7.4.2 Coprocessor Response Primitive General Format. If the coprocessor issues
this primitive with CA = 0 during a conditional category instruction, the main processor
initiates protocol violation exception processing.
The length field of the primitive format specifies the operand length, which can be from
0–255 bytes.
The main processor reads a 32-bit address from the operand address CIR. Using a series
of long-word transfers, the processor transfers the operand between this address and the
operand CIR. The DR bit determines the direction of the transfer. The processor reads or
writes the operand parts to ascending addresses, starting at the address from the operand
address CIR. If the operand length is not a multiple of four bytes, the final operand part is
transferred using a one-, two-, or three-byte transfer as required.
The function code used with the address read from the operand address CIR indicates
either supervisor or user data space according to the value of the S-bit in the
MC68020/EC020 SR.
7-40
15
CA
Figure 7-31. Take Address and Transfer Data Primitive Format
PC
14
DR
13
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Freescale Semiconductor, Inc.
For More Information On This Product,
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M68020 USER’S MANUAL
Go to: www.freescale.com
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LENGTH
MOTOROLA
0