MPC8560CPX667JC Freescale Semiconductor, MPC8560CPX667JC Datasheet - Page 79

• Manufacturer Part Number: MPC8560CPX667JC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8560CPX667JC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Rohs Compliant: No
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
PD[4:31]
Notes:
1.All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
2.Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV
3.This pin must always be pulled up to OV
4.This pin is an open drain signal.
5.This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8560 is in the
6.Treat these pins as no connects (NC) unless using debug address functionality.
7.The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
8.The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or
9.Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the V
14.Internal thermally sensitive resistor.
15.No connections should be made to these pins.
16.These pins are not connected for any functional use.
17.PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OV
18.Note that these signals are POR configurations for Rev. 1.x and notes 5 and 9 apply to these signals in Rev. 1.x but not in
19 If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a logic –1
20.Recommend a pull-up resistor (~1 KΩ) b placed on this pin to OV
21.These are test signals for factory use only and must be pulled up (100 Ω - 1 kΩ) to OVDD for normal machine operation.
22.If this signal is used as both an input and an output, a weak pull-up (~10 kΩ) is required on this pin.
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an external
device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended
to be high during reset.
resistors. See
pull-down resistors. See the
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the PCI Specification .
and regulation.
64-bit buffer mode (pins PCI_AD[63:32] and PCI_C_BE[7:4]).
later revisions.
state during reset.
Signal
Section 15.2, “Platform/System PLL
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4, AC3, AC2,
Y1, Y2, Y3, Y4, Y5, Y6, AA8, AA7, AA4, AA3, AA2,
Section 15.3, “e500 Core PLL
Table 54. MPC8560 Pinout Listing (continued)
DD
AC1, AD1, AD2, AD5, AD6, AE3, AE2
/GND planes internally and may be used by the core power supply to improve tracking
DD
.
Package Pin Number
Ratio.”
Ratio.”
DD
.
DD
.
Pin Type
I/0
Package and Pin Listings
Supply
Power
OV
DD
DD
when using
Notes
—
79