MPC8560CPX667JC Freescale Semiconductor, MPC8560CPX667JC Datasheet - Page 35

• Manufacturer Part Number: MPC8560CPX667JC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIIr

Specifications of MPC8560CPX667JC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 667MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Rohs Compliant: No
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Parameter
Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
TSEC2_TXD[6:5] = 00
TSEC2_TXD[6:5] = 11
POR Configuration
(default)
(default)
(default)
(default)
(default)
(default)
—
—
—
—
—
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
LBKHOV1
LBKHOV2
LBKHOV3
LBKHOV4
LBKHOX1
LBKHOX2
LBKHOZ1
LBIVKH1
LBIVKH2
LBIXKH1
LBIXKH2
LBOTOT
1
Min
1.8
1.7
0.5
1.0
1.5
0.7
1.6
0.7
1.6
—
—
—
—
—
Max
2.0
3.5
2.2
3.7
2.3
3.8
2.3
2.5
3.8
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Local Bus
Notes
4, 5, 8
4, 5, 8
4, 5
4, 5
4, 8
4, 8
4, 8
4, 8
4, 8
4, 8
7, 9
6
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