MPC8347CVRAGDB Freescale Semiconductor, MPC8347CVRAGDB Datasheet - Page 20

• Manufacturer Part Number: MPC8347CVRAGDB
• Description: IC MPU POWERQUICC II 620-PBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8347CVRAGDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 400MHz
• Embedded Interface Type: I2C, SPI, USB, UART
• Digital Ic Case Style: BGA
• No. Of Pins: 672
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR and DDR2 SDRAM
Figure 5
20
At recommended operating conditions with GV
266 MHz
200 MHz
MDQS preamble start
MDQS epilogue end
Notes:
1. The symbols for timing specifications follow the pattern of t
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS. For the
4. t
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that t
and t
the rising or falling edge of the reference clock (KH or KL) until the output goes invalid (AX or DX). For example, t
symbolizes DDR timing (DD) for the time t
set up (S) or output valid time. Also, t
low (L) until data outputs (D) are invalid (X) or data output hold time.
ADDR/CMD setup and hold specifications, it is assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). t
DQSS override bits in the TIMING_CFG_2 register and is typically set to the same delay as the clock adjust in the CLK_CNTL
register. The timing parameters listed in the table assume that these two parameters are set to the same adjustment value.
See the MPC8349EA PowerQUICC II Pro Integrated Host Processor Family Reference Manual for the timing modifications
enabled by use of these bits.
(MECC), or data mask (MDM). The data strobe should be centered inside the data eye at the pins of the microprocessor.
symbol conventions described in note 1.
DDKHMH
(first two letters of functional block)(reference)(state)(signal)(state)
shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (t
follows the symbol conventions described in note 1. For example, t
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
Table 20. DDR and DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
MCK[n]
MCK[n]
MDQS
MDQS
DDKLDX
Figure 5. Timing Diagram for t
DD
of (1.8 or 2.5 V) ± 5%.
MCK
symbolizes DDR timing (DD) for the time t
memory clock reference (K) goes from the high (H) state until outputs (A) are
t
Symbol
DDKHMH(min) = –0.6 ns
t
t
t
DDKHMP
DDKHME
DDKHMHmax) = 0.6 ns
t
MCK
for outputs. Output hold time can be read as DDR timing (DD) from
(first two letters of functional block)(signal)(state)(reference)(state)
1
–0.5 × t
1100
1200
–0.6
DDKHMH
Min
DDKHMH
MCK
DDKHMH
– 0.6
describes the DDR timing (DD) from the
can be modified through control of the
MCK
–0.5 × t
memory clock reference (K) goes
Max
0.6
—
—
MCK
Freescale Semiconductor
+ 0.6
DDKHMP
Unit
follows the
ns
ns
DDKHMH
for inputs
DDKHAS
Notes
6
6
).