CS80C286-16 Intersil, CS80C286-16 Datasheet - Page 38

• Manufacturer Part Number: CS80C286-16
• Description: IC CPU 16BIT 5V 16MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-16

• Processor Type: 80C286 16-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

NOTES:
18. Data is ignored.
19. First INTA cycle should have at least one wait state inserted to meet 82C59A minimum INTA pulse width.
20. Second INTA cycle must have at least one wait state inserted since the CPA will not drive A
21. Without the wait state, the 80C286 address will not be valid for a memory cycle started immediately after the second INTA cycle. The
22. LOCK is active for the first INTA cycle to prevent the 82289 from releasing the bus between INTA cycles in a multi-master system. LOCK
23. A
state. The CPU imposed one/clock delay prevents has contention between cascade address buffer being disabled by MCE ↓ and address
outputs.
82C59A also requires one wait state for minimum INTA pulse width.
is also active for the second INTA cycle.
23
-A
0
exits three-state OFF during
COD/INTA
A
D
S1 • S0
READY
23
15
LOCK
BUS CYCLE
M/IO,
INTA
DT/R
MCE
BHE
DEN
CLK
ALE
- A
- D
0
0
TYPE
WRITE CYCLE
PREVIOUS
φ1
T
C
φ2
(SEE NOTE 21)
φ1
FIGURE 29. INTERRUPT ACKNOWLEDGE SEQUENCE
φ
2 of the second T
T
S
φ2
INTA CYCLE 1
(SEE NOTE 19)
(SEE NOTE 22)
φ1
NOT READY
T
C
φ2
φ1
C
T
in the INTA cycle.
C
READY
φ2
80C286
φ1
38
T
(SEE NOTE 18)
I
φ2
DON’T CARE
φ1
DON’T CARE
T
I
φ2
φ1
T
I
φ2
23
φ1
-A
T
S
0
φ2
, BHE, and LOCK until after the first T
INTA CYCLE 2
φ1
T
C
(SEE NOTE 22)
(SEE NOTE 20)
φ2
NOT READY READY
φ1
T
C
φ2
φ1
VECTOR
T
S
φ2
C