CS80C286-16 Intersil, CS80C286-16 Datasheet - Page 36

• Manufacturer Part Number: CS80C286-16
• Description: IC CPU 16BIT 5V 16MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-16

• Processor Type: 80C286 16-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

NOTES:
11. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
12. Address, M/IO and COD/lNTA may start floating during any T
13. BHE and LOCK may start floating after the end of any T
14. The minimum HOLD to HLDA time is shown. Maximum is one T
15. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
16. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
17. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
BUS CYCLE TYPE
to external HOLD. The float starts in
external HOLD. The float starts in
Interrupts, Waits, Lock, etc.).
is ignored after ready is signaled via the asynchronous input.
BHE, LOCK
COD/INTA
SRDYEN
ARDYEN
A
D
SRDY +
ARDY +
S1 • S0
CMDLY
MWTC
23
15
HOLD
HLDA
M/IO,
DT/R
CLK
DEN
ALE
- A
- D
FIGURE 28. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
0
0
V
T
T
(SEE NOTE 11)
OH
S
C
φ1
- STATUS CYCLE
- COMMAND CYCLE
BUS HOLD ACKNOWLEDGE
T
H
φ2
(SEE NOTE 14)
φ1
φ
1 of T
φ
T
2 of T
H
φ2
C
.
C
.
φ1
T
H
φ2
C
φ1
depending on when internal 80C286 bus arbiter decides to release bus to
80C286
T
C
VALID
S
NOT READY NOT READY
DELAY ENABLE
depending on when internal 80C286 bus arbiter decides to release bus
φ2
VALID
H
36
longer.
NOT READY NOT READY
φ1
T
C
φ2
WRITE CYCLE
φ1
(SEE NOTE 12)
(SEE NOTE 13)
(SEE NOTE 15)
T
C
VALID
φ2
φ1
(SEE NOTE 17)
READY
(SEE NOTE 16)
T
C
φ2
φ1
T
I
φ2
(SEE NOTE 17)
ACKNOWLEDGE
(SEE NOTE 11)
φ1
BUS HOLD
T
H
φ2