MPC8313CVRADDB Freescale Semiconductor, MPC8313CVRADDB Datasheet - Page 27

• Manufacturer Part Number: MPC8313CVRADDB
• Description: MPU POWERQUICC II PRO 516-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8313CVRADDB

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 267MHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 516-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8313E-RDB
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: - 0.3 V to + 1.26 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 16 KB
• I/o Voltage: 2.5 V
• Interface Type: I2C, SPI, UART
• Minimum Operating Temperature: - 40 C
• Program Memory Type: EEPROM/Flash
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 14
Freescale Semiconductor
At recommended operating conditions with LV
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
Fall time (20%–80%)
GTX_CLK125 reference clock period
GTX_CLK125 reference clock duty cycle
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
2. This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns is
3. For 10 and 100 Mbps, t
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long
5. Duty cycle reference is LV
6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming convention.
RGMII and RTBI timing. For example, the subscript of t
notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols representing skews,
the subscript is skew (SK) followed by the clock that is being skewed (RGT).
added to the associated clock signal.
as the minimum duty cycle is not violated and stretching occurs for no more than three t
between.
(At Transmitter)
shows the RGMII and RTBI AC timing and multiplexing diagrams.
RXD[8:5][3:0]
RXD[7:4][3:0]
TXD[8:5][3:0]
TXD[7:4][3:0]
GTX_CLK
(At PHY)
(At PHY)
RX_CTL
RX_CLK
TX_CLK
TX_CTL
Parameter/Condition
MPC8313E PowerQUICC
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
Table 30. RGMII and RTBI AC Timing Specifications (continued)
RGT
DDA
scales to 400 ns ± 40 ns and 40 ns ± 4 ns, respectively.
/2 or LV
DDB
DDA
RXD[3:0]
TXD[3:0]
RXD[4]
TXD[4]
TXEN
RXDV
/LV
/2.
3, 5
DDB
™
of 2.5 V ± 5%.
II Pro Processor Hardware Specifications, Rev. 3
RXD[8:5]
RXD[7:4]
TXD[8:5]
TXD[7:4]
RXERR
TXERR
RXD[9]
TXD[9]
RGT
represents the RTBI (T) receive (RX) clock. Note also that the
t
t
G125H
RGTH
Symbol
t
t
t
RGTR
G12
RGTF
/t
/t
RGT
G125
6
1
t
t
SKRGT
SKRGT
t
RGTH
Ethernet: Three-Speed Ethernet, MII Management
Min
40
47
—
—
—
RGT
t
of the lowest speed transitioned
RGT
Typ
8.0
50
—
—
—
t
t
SKRGT
SKRGT
Max
0.75
0.75
60
53
—
Unit
ns
ns
ns
%
%
27