Z8L18020VSC Zilog, Z8L18020VSC Datasheet - Page 58

• Manufacturer Part Number: Z8L18020VSC
• Description: IC 20MHZ LOW PWR S180 68-PLCC
• Manufacturer: Zilog

Specifications of Z8L18020VSC

• Processor Type: Z80
• Features: Enhanced DMA Support
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

cleared to
The DMA Status Register (
disable DMA transfer and DMA termination interrupts.
and
transfer terminates (
DMAC. When
(
To perform a software
written with a
Writing
startable. Writing
automatically sets DMA Main Enable (
and
transfer terminates (
DMAC. When
(
To perform a software
written with
ing
enables channel 0 DMA and automatically sets DMA Main
Enable (
any software
0
any software
0
during the same access.
during the same access.
to
1
1
0
), a DMA interrupt request is made to the CPU.
), a DMA interrupt request is made to the CPU.
0
0
during
1
1
to
) to
disables channel 0 DMA. Writing
during the same register
, channel 1 DMA is enabled. When a DMA
, channel 0 DMA is enabled. When a DMA
0
0
1
during the same register
disables channel 1 DMA, but DMA is re-
.
to
to
0
0
to
and the DMA interrupt is enabled
and the DMA interrupt is enabled
is cleared to
1
.
, this bit should be written with
, this bit should be written with
enables channel 1 DMA and
),
),
to
to
always reads as .
always reads as .
) is used to enable and
0
is reset to
is reset to
When performing
When performing
When
When
,
,
during
) to
access. Writ-
should be
should be
1
0
0
.
access.
by the
by the
to
.
is
1
1
1
In Progress.
(indicated when
to be generated. When
mination interrupt is disabled.
(indicated when
to be generated. When
mination interrupt is disabled.
only enabled when its
channel 1) and the
When
activity during the
DMA,
if the contents are already ). This condition automatically
sets
is set to
is set to
.
.
by
to
also indicates DMA transfer status, Completed or
1
to
.
occurs,
cannot be directly written. The bit is cleared to
and/or
1
1
, allowing DMA operations to continue.
or indirectly set to
1
, the termination channel 0 of DMA transfer
, the termination channel 1 DMA transfer
is cleared to
interrupt service routine. To restart
should be written with a
0
bit is set to .
is reset to
) causes a CPU interrupt request
) causes a CPU interrupt request
bit (
0
during
0
0
1
, the channel 0 DMA ter-
, the channel 0 DMA ter-
by setting
A DMA operation is
0
for channel
, thus disabling DMA
is cleared to
is cleared to
.
0
and/or
,
W h e n
0
W h e n
0
1
ZiLOG
during
during
(even
for
0