Z8L18020VSC Zilog, Z8L18020VSC Datasheet - Page 17

IC 20MHZ LOW PWR S180 68-PLCC

Z8L18020VSC

Manufacturer Part Number
Z8L18020VSC
Description
IC 20MHZ LOW PWR S180 68-PLCC
Manufacturer
Zilog
Datasheet

Specifications of Z8L18020VSC

Processor Type
Z80
Features
Enhanced DMA Support
Speed
20MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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ZiLOG
is descended from two different “ancestor” processors,
ZiLOG’s original Z80 and the Hitachi 64180. The Operat-
ing Mode Control Register (OMCR), illustrated in Figure
8, can be programmed to select between certain Z80 and
64180 differences.
The Z8S180/Z8L180
set to a
When
code fetch cycles, Interrupt Acknowledge cycles, and the
first machine cycle of an
On the Z8S180/Z8L180, this choice makes the processor
fetch a
from a zero-wait-state memory location, the processor uses
three clock bus cycles. These bus cycles are not fully Z80-
timing compatible.
When
ing the instruction fetch cycles. After fetching a
struction with normal timing, the processor goes back and
refetches the instruction using fully Z80-compatible cycles
that include driving
by some external Z80 peripherals to properly decode the
quence when
instruction. Figure 9 and Table 5 show the
1
during
instruction one time. When fetching a
1
0
, the
, the processor does not drive
is
This bit controls the
0
.
Low. This option may be required
output is asserted Low during op-
.
acknowledge.
output and is
Low dur-
se-
in-

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