MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 32

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

USB
Figure 16
9
This section provides the AC and DC electrical characteristics for the USB dual-role controllers.
32
MDC rise time (20%–80%)
MDC fall time (80%–20%)
Note:
1
2
3
4
5
The symbols used for timing specifications herein follow the pattern of t
for inputs and t
management data timing (MD) for the time t
hold time. Also, t
latter convention is used with the appropriate letter: R (rise) or F (fall).
This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
divided by 64.)
This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency
is 8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and
the minimum frequency is 1.7 MHz.)
Guaranteed by design.
t
valid state (V) relative to the t
plb_clk
USB
is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
shows the MII management AC timing diagram.
Parameter
(first two letters of functional block)(reference)(state)(signal)(state)
MDDVKH
(Output)
(Input)
MDIO
MDIO
MDC
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Table 33. MII Management AC Timing Specifications (continued)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the
Figure 16. MII Management Interface Timing Diagram
MDC
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the
Symbol
t
MDCH
t
t
MDCR
MDCF
t
MDDVKH
MDC
t
1
MDC
t
MDKHDX
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data
Min
—
—
t
MDCF
for outputs. For example, t
(first two letters of functional block)(signal)(state) (reference)(state)
Typical
t
MDDXKH
—
—
t
MDCR
Max
10
10
MDKHDX
Freescale Semiconductor
symbolizes
Unit
ns
ns
Notes
4
4