MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 103

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

22.3
Table 77
Freescale Semiconductor
Note:
1
2
3
4
5
6
Ref
Note:
1
25.0
25.0
33.3
33.3
48.0
66.7
25.0
33.3
50.0
50.0
66.7
66.7
66.7
Values in MHz.
System PLL VCO range: 400–800 MHz.
CSB frequencies less than 133 MHz will not support Gigabit Ethernet rates.
Minimum data rate for DDR2 is 250 MHz and for DDR1 is 167 MHz.
Applies to DDR2 only.
Applies to eLBC PLL-enabled mode only.
Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be set properly so that the core VCO
frequency is in the range of 800–1600 MHz.
1
0–1
00
01
10
LBCM DDRCM SVCOD SPMF
0
0
0
0
0
0
0
0
0
0
0
0
0
shows suggested PLL configurations for different input clocks (LBCM = 0).
Suggested PLL Configurations
RCWLR[COREPLL]
1
1
1
1
1
1
0
0
0
0
0
0
0
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
0100
0100
0100
2–5
2
2
2
2
2
2
4
2
4
2
2
2
2
Table 76. e300 Core PLL Configuration (continued)
Table 77. Example Clock Frequency Combinations
5
6
5
4
3
2
8
8
4
8
4
5
6
6
0
0
0
VCO
Sys
500
600
667
533
576
533
800
533
800
800
533
667
800
1,
2
CSB
266.7
266.7
125
150
167
133
144
133
200
200
400
333
400
1
core_clk : csb_clk Ratio
,3
DDR data
rate
400
400
250
300
333
267
288
266
200
267
200
267
333
1,
5
5
4
4:1
4:1
4:1
83.3
100
133
100
133
62.5
66.7
66.7
75
72
—
—
—
/2
6
6
6
6
6
6
6
eLBC
83.3
100
100
31.3
37.5
41.6
33.3
33.3
66.7
66.7
36
50
50
/4
6
6
6
1
15.6
18.8
20.8
16.7
16.7
33.3
33.3
41.6
18
25
25
50
50
/8
333
400
× 1
—
—
—
—
—
—
—
—
—
—
—
VCO Divider
× 1.5
400
600
400
500
600
—
—
—
—
—
—
—
—
e300 Core
2
4
8
333
400
533
400
800
533
667
800
× 2
—
—
—
—
—
× 2.5
1
375
416
333
360
333
500
667
500
667
1
—
—
—
—
Clocking
375
450
500
400
432
400
600
800
600
800
× 3
—
—
—
103