MPC8379EVRAJF Freescale Semiconductor, MPC8379EVRAJF Datasheet - Page 102

• Manufacturer Part Number: MPC8379EVRAJF
• Description: MPU PWRQUICC II 533MHZ 689TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC II PROr

Specifications of MPC8379EVRAJF

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 689-TePBGA II
• Maximum Clock Frequency: 533 MHz
• Operating Supply Voltage: 1.8 V to 2.5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Program Memory Size: 64KB
• Cpu Speed: 533MHz
• Embedded Interface Type: DUART, HSSI, I2C, IPIC, JTAG, SPI, USB
• Digital Ic Case Style: BGA
• No. Of Pins: 689
• Rohs Compliant: Yes
• For Use With: MPC8377E-RDBA - BOARD REF DES MPC8377 REV 2.1MPC8377E-MDS-PB - BOARD MODULAR DEV SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
1
2
22.2
RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the
e300 core clock (core_clk).
that are not listed in
102
CFG_CLKIN_DIV doubles csb_clk if set high.
CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
0–1
nn
11
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
Core PLL Configuration
RCWLR[COREPLL]
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MHz.
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Table 76
nnnn
0000
0001
0001
0001
0001
0001
0001
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
2–5
Table 76
should be considered as reserved.
Table 76. e300 Core PLL Configuration
6
0
n
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
shows the encodings for RCWLR[COREPLL]. COREPLL values
(PLL off, csb_clk clocks core directly)
core_clk : csb_clk Ratio
NOTE
PLL bypassed
1.5:1
1.5:1
1.5:1
2.5:1
2.5:1
2.5:1
3.5:1
3.5:1
3.5:1
n/a
1:1
1:1
1:1
2:1
2:1
2:1
3:1
3:1
3:1
(PLL off, csb_clk clocks core
Freescale Semiconductor
VCO Divider
PLL bypassed
directly)
n/a
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
1