MPC857DSLVR50B Freescale Semiconductor, MPC857DSLVR50B Datasheet - Page 46

• Manufacturer Part Number: MPC857DSLVR50B
• Description: IC MPU POWERQUICC 50MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC857DSLVR50B

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Processor Series: MPC85xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Operating Supply Voltage: 2.5 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.465/3.6V
• Operating Supply Voltage (min): 2/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 357
• Package Type: BGA
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CPM Electrical Characteristics
11 CPM Electrical Characteristics
This section provides the AC and DC electrical specifications for the communications processor module
(CPM) of the MPC862/857T/857DSL.
11.1
Table 14
46
1
Num
t3 = Specification 23
21
22
23
24
25
26
27
28
29
30
31
provides the PIP/PIO AC timings as shown in
PIP/PIO AC Electrical Specifications
DATA-IN
Data-in setup time to STBI low
Data-in hold time to STBI high
STBI pulse width
STBO pulse width
Data-out setup time to STBO low
Data-out hold time from STBO high
STBI low to STBO low (Rx interlock)
STBI low to STBO high (Tx interlock)
Data-in setup time to clock high
Data-in hold time from clock high
Clock low to data-out valid (CPU writes data, control, or direction)
STBO
STBI
MPC862/857T/857DSL PowerQUICC™ Family Hardware Specifications, Rev. 3
Figure 40. PIP Rx (Interlock Mode) Timing Diagram
Characteristic
21
27
Table 14. PIP/PIO Timing
Figure 40
23
24
though
1 clk – 5 ns
2.5 – t3
Figure
Min
22
1.5
7.5
All Frequencies
—
15
—
0
2
5
2
1
44.
Freescale Semiconductor
Max
25
—
—
—
—
—
—
—
—
—
2
Unit
clk
clk
clk
clk
clk
clk
ns
ns
ns
ns
ns