A80386DX16 Intel, A80386DX16 Datasheet - Page 82

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

Intel386
2) The next address may appear as early as the bus
3) Once NA
82
Following any idle bus state (Ti) the address is always non-pipelined and NA
after an idle state requires a non-pipelined cycle with at least one wait state (cycle 1 above)
The pipelined cycles (2 3 4 above) are shown with various numbers of wait states
state after NA
ures 5-16 or 5-17) In that case state T2P is en-
tered immediately However when there is not an
internal bus request already pending the next ad-
dress will not be available immediately after NA
is asserted and T2I is entered instead of T2P (see
Figure 5-19 Cycle 3) Provided the current bus cy-
cle isn’t yet acknowledged by READY
T2P will be entered as soon as the Intel386 DX
does drive the next address External hardware
should therefore observe the ADS
confirmation the next address is actually being
driven on the bus
commits itself to the highest priority bus request
that is pending internally It can no longer perform
another 16-bit transfer to the same address should
BS16
TM
be asserted externally so thereafter
DX MICROPROCESSOR
Figure 5-17 Fastest Transition to Pipelined Address Following Idle Bus State
is sampled asserted the Intel386 DX
was sampled asserted (see Fig-
output as
asserted
4) Any address which is validated by a pulse on the
5) Only the address and bus cycle definition of the
must assume the current bus size is 32 bits
Therefore if NA
that bus cycle (see Figures 5-16 5-17 5-19)
Consequently do not assert NA
See 5 4 3 6 Dynamic Bus Sizing with Pipelined
Address
Intel386 DX ADS
the address pins for at least two processor clock
periods The Intel386 DX cannot produce a new
address more frequently than every two proces-
sor clock periods (see Figures 5-16 5-17 5-19)
very next bus cycle is available The pipelining ca-
pability cannot look further than one bus cycle
ahead (see Figure 5-19 Cycle 1)
bus cycle BS16
cles which must have BS16
is only sampled during wait states To start address pipelining
must be negated thereafter in
is sampled asserted within a
output will remain stable on
driven asserted
during bus cy-
231630 –21