A80386DX16 Intel, A80386DX16 Datasheet - Page 55

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

4 5 4 Translation Lookaside Buffer
The Intel386 DX paging hardware is designed to
support demand paged virtual memory systems
However performance would degrade substantially
if the processor was required to access two levels of
tables for every memory reference To solve this
problem the Intel386 DX keeps a cache of the most
recently accessed pages this cache is called the
Translation Lookaside Buffer (TLB) The TLB is a
four-way set associative 32-entry page table cache
It automatically keeps the most commonly used
Page Table Entries in the processor The 32-entry
TLB coupled with a 4K page size results in cover-
age of 128K bytes of memory addresses For many
common multi-tasking systems the TLB will have a
hit rate of about 98% This means that the proces-
sor will only have to access the two-level page struc-
ture on 2% of all memory references Figure 4-22
illustrates how the TLB complements the Intel386
DX’s paging mechanism
4 5 5 Paging Operation
The paging hardware operates in the following fash-
ion The paging unit hardware receives a 32-bit lin-
ear address from the segmentation unit The upper
20 linear address bits are compared with all 32 en-
tries in the TLB to determine if there is a match If
there is a match (i e a TLB hit) then the 32-bit phys-
ical address is calculated and will be placed on the
address bus
However if the page table entry is not in the TLB
the Intel386 DX will read the appropriate Page Direc-
tory Entry If P
cating that the page table is in memory then the
Intel386 DX will read the appropriate Page Table En-
Figure 4-22 Translation Lookaside Buffer
e
1 on the Page Directory Entry indi-
231630– 68
try and set the Access bit If P
Table Entry indicating that the page is in memory
the Intel386 DX will update the Access and Dirty bits
as needed and fetch the operand The upper 20 bits
of the linear address read from the page table will
be stored in the TLB for future accesses However if
P
Page Table Entry then the processor will generate a
page fault an Exception 14
The processor will also generate an exception 14
page fault if the memory reference violated the
page protection attributes (i e U S or R W) (e g try-
ing to write to a read-only page) CR2 will hold the
linear address which caused the page fault If a sec-
ond page fault occurs while the processor is at-
tempting to enter the service routine for the first
then the processor will invoke the page fault (excep-
tion 14) handler a second time rather than the dou-
ble fault (exception 8) handler Since Exception 14 is
classified as a fault CS EIP will point to the instruc-
tion causing the page fault The 16-bit error code
pushed as part of the page fault handler will contain
status bits which indicate the cause of the page
fault
The 16-bit error code is used by the operating sys-
tem to determine how to handle the page fault Fig-
ure 4-23A shows the format of the page-fault error
code and the interpretation of the bits
Even though the bits in the error code (U S W R
and P) have similar names as the bits in the Page
Directory Table Entries the interpretation of the er-
ror code bits is different Figure 4-23B indicates
what type of access caused the page fault
U S The U S bit indicates whether the access
causing the fault occurred when the processor was
executing in User Mode (U S
mode (U S
W R The W R bit indicates whether the access
causing the fault was a Read (W R
(W R
P The P bit indicates whether a page fault was
caused by a not-present page (P
level protection violation (P
U UNDEFINED
15
U U U U U U U U U U U U U U
e
Figure 4-23A Page Fault Error Code Format
0 for either the Page Directory Entry or the
e
1)
Intel386
e
0)
TM
NOTE
DX MICROPROCESSOR
e
e
1)
1) or in Supervisor
e
e
0) or by a page
e
1 on the Page
0) or a Write
3 2 1 0
U
S R
W P
55