A80386DX16 Intel, A80386DX16 Datasheet - Page 37

• Manufacturer Part Number: A80386DX16
• Description: IC MPU 32-BIT 5V 16MHZ 132-PGA
• Manufacturer: Intel

Specifications of A80386DX16

• Processor Type: 386DX
• Features: 32-bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-PGA
• Family Name: Intel386 DX
• Device Core Size: 32b
• Frequency (max): 16MHz
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 132
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 807050

GDT Generally the GDT contains code and data
segments used by the operating systems and task
state segments and descriptors for the LDTs in a
system
The first slot of the Global Descriptor Table corre-
sponds to the null selector and is not used The null
selector defines a null pointer value
4 3 3 3 LOCAL DESCRIPTOR TABLE
LDTs contain descriptors which are associated with
a given task Generally operating systems are de-
signed so that each task has a separate LDT The
LDT may contain only code data stack task gate
and call gate descriptors LDTs provide a mecha-
nism for isolating a given task’s code and data seg-
ments from the rest of the operating system while
the GDT contains descriptors for segments which
are common to all tasks A segment cannot be ac-
cessed by a task if its segment descriptor does not
exist in either the current LDT or the GDT This pro-
vides both isolation and protection for a task’s seg-
ments while still allowing global data to be shared
among tasks
Unlike the 6 byte GDT or IDT registers which contain
a base address and limit the visible portion of the
LDT register contains only a 16-bit selector This se-
lector refers to a Local Descriptor Table descriptor in
the GDT
4 3 3 4 INTERRUPT DESCRIPTOR TABLE
The third table needed for Intel386 DX systems is
the Interrupt Descriptor Table (See Figure 4-4 ) The
IDT contains the descriptors which point to the loca-
tion of up to 256 interrupt service routines The IDT
BASE
LIMIT
P
DPL
S
TYPE
A
G
D
0
AVL
31
SEGMENT BASE 15
BASE 31
NOTE
In a maximum-size segment (ie a segment with G
segment base should be zero (ie segment base 11 000
Base Address of the segment
The length of the segment
Present Bit
Descriptor Privilege Level 0– 3
Segment Descriptor
Type of Segment
Accessed Bit
Granularity Bit
Default Operation Size (recognized in code segment descriptors only)
Bit must be zero (0) for compatibility with future processors
Available field for user or OS
24
G
1
e
1
Present
e
D
0
Segment length is page granular
0
e
0
System Descriptor
0
e
AVL
Not Present
Figure 4-5 Segment Descriptors
19
LIMIT
16
1
e
e
Code or Data Segment Descriptor
SEGMENT LIMIT 15
P
1 and segment limit 19 0
0
e
e
Segment length is byte granular
DPL
000H)
may contain only task gates interrupt gates and
trap gates The IDT should be at least 256 bytes in
size in order to hold the descriptors for the 32 Intel
Reserved Interrupts Every interrupt used by a sys-
tem must have an entry in the IDT The IDT entries
are referenced via INT instructions external inter-
rupt vectors and exceptions (See 2 9 Interrupts)
4 3 4 Descriptors
4 3 4 1 DESCRIPTOR ATTRIBUTE BITS
The object to which the segment selector points to
is called a descriptor Descriptors are eight byte
quantities which contain attributes about a given re-
gion of linear address space (i e a segment) These
attributes include the 32-bit base linear address of
the segment the 20-bit length and granularity of the
segment the protection level read write or execute
privileges the default size of the operands (16-bit or
S
1
e
Figure 4-4 Interrupt Descriptor
32-bit segment
Intel386
TYPE
0
Table Register Use
e
FFFFFH) the lowest 12 bits of the
TM
0
DX MICROPROCESSOR
e
A
16-bit segment
23
BASE
16
0
ADDRESS
231630 –58
BYTE
a
0
4
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